20 Dec
2007
20 Dec
'07
1:30 a.m.
That's BSCP as in "Bit-Serial Computer Project." The 2N2/256 part of
the name is a nod to ham homebrewer Jim Kortge (K8IQY) who designed a
QRP rig called the 2N2/40 for a design contest about ten years ago.
The contest objective was to design and build a functional amateur
radio transceiver, using a maximum of twenty-two 2N2222 type
transistors.
Whether it uses drums, disks, or ultrasonic delay lines, my challenge
is:
1) To build a complete functional computer, including memory,
using no more than 256 2N2222-ish transistors (plus scads of diodes,
resistors, etc.).
2) Use no ICs or other parts that wouldn't have been available
to hobbyists ca. 1965.
3) Must be transportable in the boot of a mid-size sedan (i.e.
a few roughly 350mm cubical modules).
Anybody up for a contest to see who can design the most powerful
general-purpose digital computer given these constraints? I guess
we'd have to figure out what "powerful" means in this context, given
that it's likely never to exceed a few KIPS.
I'm prototyping DTL NAND gates and flip-flops today...
-Bobby
20 Dec
20 Dec
3:11 a.m.
Robert Nansel wrote:
That's BSCP as in "Bit-Serial Computer
Project." The 2N2/256 part of the
name is a nod to ham homebrewer Jim Kortge (K8IQY) who designed a QRP
rig called the 2N2/40 for a design contest about ten years ago. The
contest objective was to design and build a functional amateur radio
transceiver, using a maximum of twenty-two 2N2222 type transistors.
Whether it uses drums, disks, or ultrasonic delay lines, my challenge is:
1) To build a complete functional computer, including memory, using
no more than 256 2N2222-ish transistors (plus scads of diodes,
resistors, etc.).
2) Use no ICs or other parts that wouldn't have been available to
hobbyists ca. 1965.
3) Must be transportable in the boot of a mid-size sedan (i.e. a
few roughly 350mm cubical modules).
Anybody up for a contest to see who can design the most powerful
general-purpose digital computer given these constraints? I guess we'd
have to figure out what "powerful" means in this context, given that
it's likely never to exceed a few KIPS.
I'm prototyping DTL NAND gates and flip-flops today...
Rather than a magnetic drum, I think a much more achievable contraption
is a drum that uses capacitance for storage. The density would be much
lower, but it would be more tractable, I think.
Inside a hollow cylinder mount rows of capacitors. One side of all
capacitors would be connected in common to ground, which conveniently
would also be the axle that would be spinning the drum. The other side
of each cap would punch through the cylinder wall with a brass stud. A
row of brushes would make contact with a row of caps at a given time.
Just like a DRAM, you'd have to read, sense, and refresh the caps on
each read, and every so often in case a given word wasn't read for a
while. To make things simple, read, sense, and refresh every rotation
to get rid of any special cases.
If you don't want word parallel access, then just have the studs from a
given brush represent the bits of a word. Different brushes are used to
select which word you care to access. 16 words of 16 bits should be
do-able. Thinking a bit more about this, it should be possible to make
a single cross section "slice", and then laminate these to as many words
as you'd like. The first slice would be unique -- it wouldn't have any
storage, but instead would be the clock source, and some indication of
the rotation phase (perhaps just a "this is bit 0" signal). By making
the "studs" on this clock track smaller and centered relative to the
ones used for accessing the data, you should be able to use it to gate
the r/m/w timing.
It sure isn't going to do 3000 RPM, but perhaps 1/10 of that speed, and
it will make a nice clatter I suppose. But since you are setting a
limit of 256 transistors, you shouldn't really be aiming for high
performance anyway.
4:01 a.m.
Jim Battle wrote:
Robert Nansel wrote:
IMHO, to build anything
interesting and useful, the rules should be 256
2n2222s for the CPU. The memory design requirements, (unless you're
looking to build a CARDIAC clone with 10 cells)
should allow use of contemporary memory ( but not too much, just for
code, not ALU lookup tables). The guy that did the relay computer
allowed that, and he was able to execute interesting code?.
This kind of a CPU design screams bit serial execution. Take a look at
the Nebula design (OSU) on bitsavers for insight.
Cheers,
Jim Davis.
I've been thinking about a eprom/latch/sequencer based CPU since I
picked up a hundred or so 16 bit wide 64KW eproms from a dumpster at work.
That's BSCP as in "Bit-Serial Computer
Project." The 2N2/256 part of
the name is a nod to ham homebrewer Jim Kortge (K8IQY) who designed a
QRP rig called the 2N2/40 for a design contest about ten years ago.
The contest objective was to design and build a functional amateur
radio transceiver, using a maximum of twenty-two 2N2222 type
transistors.
Whether it uses drums, disks, or ultrasonic delay lines, my challenge
is:
1) To build a complete functional computer, including memory,
using no more than 256 2N2222-ish transistors (plus scads of diodes,
resistors, etc.).
2) Use no ICs or other parts that wouldn't have been available
to hobbyists ca. 1965.
3) Must be transportable in the boot of a mid-size sedan (i.e. a
few roughly 350mm cubical modules).
Anybody up for a contest to see who can design the most powerful
general-purpose digital computer given these constraints? I guess
we'd have to figure out what "powerful" means in this context, given
that it's likely never to exceed a few KIPS.
I'm prototyping DTL NAND gates and flip-flops today...
<snip archaric
memory design considerations( another project? ) >
4:12 a.m.
davis wrote:
<snip>
IMHO, to build anything interesting and useful, the
rules should be
256 2n2222s for the CPU. The memory design requirements, (unless
you're looking to build a CARDIAC clone with 10 cells)
should allow use of contemporary memory ( but not too much, just for
code, not ALU lookup tables). The guy that did the relay computer
allowed that, and he was able to execute interesting code?.
This kind of a CPU design screams bit serial execution. Take a look at
the Nebula design (OSU) on bitsavers for insight.
Cheers,
Jim Davis.
I've been thinking about a eprom/latch/sequencer based CPU since I
picked up a hundred or so 16 bit wide 64KW eproms from a dumpster at
work.
Sorry, that's the Oregon state archive. Still, even without my
complaints, it sounds like fun and a great way to wreck any
relationships and careers.
Jim Davis.
5:01 p.m.
On Thu, 20 Dec 2007 01:01:07 -0800
davis <davis at saw.net> wrote:
I've been thinking about a eprom/latch/sequencer
based CPU since I
picked up a hundred or so 16 bit wide 64KW eproms from a dumpster at
work.
IIRC MyCPU uses microcode in an EPROM and is similar to the 6502...
http://www.mycpu.eu/
--
tsch??,
Jochen
Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/
4:58 a.m.
Jim Battle wrote:
Rather than a magnetic drum, I think a much more achievable contraption
is a drum that uses capacitance for storage. The density would be much
lower, but it would be more tractable, I think.
Inside a hollow cylinder mount rows of capacitors. One side of all
capacitors would be connected in common to ground, which conveniently
would also be the axle that would be spinning the drum. The other side
of each cap would punch through the cylinder wall with a brass stud. A
row of brushes would make contact with a row of caps at a given time.
Just like a DRAM, you'd have to read, sense, and refresh the caps on
each read, and every so often in case a given word wasn't read for a
while. To make things simple, read, sense, and refresh every rotation
to get rid of any special cases.
The ABC (Atanasoff-Berry Computer) did this in 1939-41 (you may be aware,
but figured it should be mentioned..).
4:57 a.m.
Robert Nansel wrote:
I'm prototyping DTL NAND gates and flip-flops
today...
There is a DTL AND-NOR construct requiring only one transistor that was fairly
common back in the discrete days if you're interested or unaware. Should save
transistors, but wants a neg-bias supply.
Anybody up for a contest to see who can design the
most powerful
general-purpose digital computer given these constraints? I guess
we'd have to figure out what "powerful" means in this context, given
that it's likely never to exceed a few KIPS.
Sounds like fun, even if only to do the design, but I think I must refrain
from getting sidetracked from other projects that
I've got to finish this
winter or they'll just languish for longer
('ooooh, look .. another shiny
object' syndrome).
7:55 a.m.
On Dec 20, 2007, at 1:30 AM, Robert Nansel wrote:
Anybody up for a contest to see who can design the
most powerful
general-purpose digital computer given these constraints? I guess
we'd have to figure out what "powerful" means in this context, given
that it's likely never to exceed a few KIPS.
Well then you'd have the problem of defining "most powerful". By
many metrics, any VAX is an incredibly powerful system, but the average
not-so-powerful modern PeeCee will blow its doors off in integer
performance. So how will you define "power"?
-Dave
--
Dave McGuire
Port Charlotte, FL
11:29 a.m.
On Thursday 20 December 2007 07:55, Dave McGuire wrote:
On Dec 20, 2007, at 1:30 AM, Robert Nansel wrote:
The "power" of a machine tends to directly relate to the Watts of power
it consumes from an AC supply. :)
Pat
--
Purdue University ITAP/RCAC --- http://www.rcac.purdue.edu/
The Computer Refuge --- http://computer-refuge.org
Anybody up for a contest to see who can design
the most powerful
general-purpose digital computer given these constraints? I guess
we'd have to figure out what "powerful" means in this context,
given that it's likely never to exceed a few KIPS.
Well then you'd have the problem of defining "most powerful". By
many metrics, any VAX is an incredibly powerful system, but the
average not-so-powerful modern PeeCee will blow its doors off in
integer performance. So how will you define "power"?
-Dave 
3:50 p.m.
Whether it uses drums, disks, or ultrasonic delay
lines, my challenge
is:
1) To build a complete functional computer, including memory,
Are things like core-on-a-rope ROM allowrd?
using no more than 256 2N2222-ish transistors (plus
scads of diodes,
resistors, etc.).
Do all transsitors have to be of the same flavour, or could I use TUNs
and TUPs?
I think I'd start by readign the schematics of the HP9100. It contains
more transistors than that, but it's still amazingly simple.
Anyway, the flip-flops in that machine were JKs, using 4 transsitors
each. The inputs are current-operated (direct onto the base of the
transistor). The loric gates use just diodes and resisitors, remeber you
get Q and Q/ from a flip-flop, which can really save inverters.
2) Use no ICs or other parts that wouldn't have been available
to hobbyists ca. 1965.
So that preumably means a multi-layer-PCB acting as an
inductively-coupled ROM is out. Rats!
3) Must be transportable in the boot of a mid-size sedan (i.e.
Totally OT, but I find 'boot of a sedan' a somewhat odd expession. 'Trunk
of a sedan' or 'boot of a saloon car' would seem more natural.
-tony
6060
days inactive
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days old
9 comments
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participants (8)
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ard＠p850ug1.demon.co.uk -
bnansel＠bigpond.net.au -
davis＠saw.net -
frustum＠pacbell.net -
hilpert＠cs.ubc.ca -
jkunz＠unixag-kl.fh-kl.de -
mcguire＠neurotica.com -
pat＠computer-refuge.org