80186 and now AMY chip - test-drb@ccmp.vtda.org

26 Nov 2000

From: Eric J. Korpela &lt;korpela(a)ellie.ssl.berkeley.edu&gt;

...
 I for one would be interested in seeing whatever
references to 8080 internals
...
 this kind of stuff comes from.  The bulk of what I have
doesn't give any
internal details.  I'd alway assumed that there was some sort of
synchronization of writeback to the accumulator (or other destination register)
...
 or the update of the flags that ate up the extra cycle.

On the 8080 you have cycles that are 3-6 clocks long and total
cycles(clocks).
IE: to fetch a 3byte operand like a LXI SP,1234 requires 3 CYCLES and
and an extra clock to put it in the SP.  Still thats only 10 clocks.

an an ADD REG is only one cycle and 4 clocks, the address and staus out
eat two clocks with status availabile on the midpoint of the second
clock.
The remaining clocks, T3 is the instruction decode time and T4 is the
actual
operation.

For DAD (16bit add) 10 cycles breaks to the first 3 as setup and exectute
overhead and 6 (basically two 8bit adds) spread across thre cycles. The
second two cycles have one clock each of over head as the internal bus
is used to transfer status to the out side world (bus idle state).

...
 Given a 16 bit add takes 11 T cycles, that would be 2
for fetch and decode,

not for the 8080, it's 10.  For z80 it's 11.

...
 4 for ALU passes, and 5 for who knows what.  Probably
moving things too and
...
 from internal registers, that would explain why a 16
bit increment could be
...
 done in 6 T cycles, 2 fetch+4 ALU passes. 

keep in mind the internal busses are few, so if status has to be moved to
to the TEMP for a bit test the bus takes a cycle.  Z80 adds little
overheads
like refresh (ever wonder what bus is used to get R tot he low address
bus?).

Allison