21 Apr
2016
21 Apr
'16
1:36 p.m.
A friend building a Z80 system asked me about whether the Z80 /WAIT
signal has any effect during machine cycles that aren't
memory/IO/intack cycles (i.e., neither /MREQ and /IORQ asserted). The
user manual only describes the use of /WAIT for adding wait states, so
I expect it probably only affects mem/IO/intack cycles, but I can't
find anything definitive in the user manual.
I'm hoping someone can save me the time of hooking up a logic analyzer
and running the experiment.
Thanks!
Eric
21 Apr
21 Apr
3:03 p.m.
I do know that the Wait signal was used by the Fluke 90 tester so it could be clamped on
top of an in circuit Z80 and run memory and I/O tests while the CPU was doing its regular
operations.
On vacation so haven't easy access to the operators manual for the Fluke 90 though...
John :-#)#
On Apr 21, 2016, at 1:36 PM, Eric Smith <spacewar
at gmail.com> wrote:
A friend building a Z80 system asked me about whether the Z80 /WAIT
signal has any effect during machine cycles that aren't
memory/IO/intack cycles (i.e., neither /MREQ and /IORQ asserted). The
user manual only describes the use of /WAIT for adding wait states, so
I expect it probably only affects mem/IO/intack cycles, but I can't
find anything definitive in the user manual.
I'm hoping someone can save me the time of hooking up a logic analyzer
and running the experiment.
Thanks!
Eric
22 Apr
22 Apr
12:18 a.m.
On 04/21/2016 12:36 PM, Eric Smith wrote:
A friend building a Z80 system asked me about whether
the Z80 /WAIT
signal has any effect during machine cycles that aren't
memory/IO/intack cycles (i.e., neither /MREQ and /IORQ asserted). The
user manual only describes the use of /WAIT for adding wait states, so
I expect it probably only affects mem/IO/intack cycles, but I can't
find anything definitive in the user manual.
Oh, boy! I ought to know this one, but really don't. I
never tried to use it except on some kind of data cycle.
It could, possibly, depend on what implementation of the
Z-80 you are using. I built some battery-powered stuff
using a Harris Z-80 clone that was all CMOS. Some timings
were a bit different from a Zilog Z-80.
Jon
5:15 a.m.
On 22/04/2016 3:06 AM, Eric Smith wrote:
A friend building a Z80 system asked me about whether
the Z80 /WAIT
signal has any effect during machine cycles that aren't
memory/IO/intack cycles (i.e., neither /MREQ and /IORQ asserted). The
user manual only describes the use of /WAIT for adding wait states,
so I expect it probably only affects mem/IO/intack cycles, but I
can't find anything definitive in the user manual.
I'm hoping someone can save me the time of hooking up a logic
analyzer and running the experiment.
Thanks! Eric
http://kaput.homeunix.org/~thrashbarg/z80.pdf
Looking at this Z80 datasheet (page 20 of the PDF) the timing diagrams
say the /WAIT signal is sampled on the falling edge of clock state T2.
If it is active, additional cycles are introdced between T2 and T3. This
only occurs on op-code fetch, memory reference, input-output and
interrupt acknowledge cycles.
Alexis.
2:26 p.m.
On Fri, Apr 22, 2016 at 3:15 AM, Alexis Kotlowy
<thrashbarg at kaput.homeunix.org> wrote:
http://kaput.homeunix.org/~thrashbarg/z80.pdf
Looking at this Z80 datasheet (page 20 of the PDF) the timing diagrams
say the /WAIT signal is sampled on the falling edge of clock state T2.
If it is active, additional cycles are introdced between T2 and T3. This
only occurs on op-code fetch, memory reference, input-output and
interrupt acknowledge cycles.
Thanks, but I'm not convinced by that particular part of the
datasheet. I see where it says:
1) "The Z80 CPU executes instruction by proceeding through a specific
sequence of operations: *Memory read or write *I/O device read or
write *Interrupt acknowledge"
2) "Machine cycles can be extended [...] by the insertion of one or
more Wait states by the user."
The first of those statements omits that there can be M cycles which
are of none of those stated cycle types, and are used purely for
internal operation. For example, an ADD HL, BC instruction has three M
cycles, but only the first is a fetch, and the other are internal
operations. The second and third M cycles have seven T-states between
them; probably one of those M cycles has three T-states and the other
has four[*].
I don't see where it says that ONLY the op-code fetch, memory
reference, input-output, and interrupt cycles can be extended, and I
don't see anything in the datasheet or user manual that definitively
states that the second and third M cycle of that 16-bit ADD
instruction can't be extended with wait states by /WAIT being asserted
at the faling edge of T2 of those M cycles.
On the other hand, if someone with personal experience has verified
that internal-only M cycles can't be extended by asserting /WAIT,
that's would answer my question. I'm starting to think that I'll
actually have to kludge up a test circuit to find out.
Best regards,
Eric
[*] I thought at one point I saw Zilog or Mostek Z80 documentation
that gave the specific details of every M cycle of every instruction,
but I can find such a thing at the moment. :-(
23 Apr
23 Apr
3:59 a.m.
On Fri, Apr 22, 2016 at 12:26 PM, Eric Smith <spacewar at gmail.com> wrote:
I thought at one point I saw Zilog or Mostek Z80
documentation
that gave the specific details of every M cycle of every instruction,
but I can find such a thing at the moment. :-(
Found it. Section 12.0 of the Mostek MK3880 Central Processing Unit
Technical Manual, as found in the Mostek Microcomputer Z80 Data Book,
publication number 79602, August 1978. Also in the Mostek 1982/83 Z80
Designer's Guide, June 1982.
I'm still looking for the Z80 DMA Technical Manual. **NOT** the data
sheet, I've got multiple copies of that.
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