CPU design at the gate level - test-drb@ccmp.vtda.org

5 Nov 2001

Yes but I was working on the presumption of xN=8
and for every permutation of 8bit A and 8bit B.

Allison
-----Original Message-----
From: Greg Ewing &lt;greg(a)cosc.canterbury.ac.nz&gt;
To: classiccmp(a)classiccmp.org &lt;classiccmp(a)classiccmp.org&gt;
Date: Monday, November 05, 2001 11:41 PM
Subject: Re: CPU design at the gate level

...
 ajp166 &lt;ajp166(a)bellatlantic.net&gt;et>:

  Whats
 problemtic is that the ALU must do about 8-16 different operations
 so that would be at least a 512kN part or larger. 
Not that big, surely? 4 A inputs, 4 B inputs, carry input,
4 function select inputs comes to 13 inputs, so 8KxN
should be enough.

Greg Ewing, Computer Science Dept, +--------------------------------------+
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