Subject: Re: TTL homebrew CPUs
From: woodelf <bfranchuk at jetnet.ab.ca>
Date: Tue, 10 Jul 2007 11:04:27 -0600
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
dwight elvey wrote:
Right now, we are at the power density limits for
uP's. We can
build smaller ones and put more circuits on a chip but we've
hit the limits of power density. We get smaller improvements
from lower K insulation on wiring but power is now the wall.
Dwight
Does this mean that if we reduce the number of transistors
we can go faster? Let see a PDP 8/Z(1) with current technology
would be? :) I think the problem is computer design rather
than the chip design -- You don't have random access memory
any more & salesmen push clock speed rather than a usefull
measure of computing power.
(1) Zippy - 1000x faster the a PDP 8/E.
Now back to thinking about how to build a homebrew CPU...
Front panel or no Front panel.
The pdp8 limitation back then was not the CPU but the fact
that it's timing was interlocked with the core. Take core
out of the timing picture with fast Sram and crank it up
then things like bus timing and ripple carry are a factor.
So a turbo PDP-8 is achieveable and if it were all on a chip
your "8/Z" would be scary fast with current tech.
However if you reduce the number of transistors as MIPS and
other RISC machines early on did your dependent on raw speed
at the die level and the cycle repeats. That is you end up
pushing for ever higher speeds to make up for simplicity and
those transistors left are hitting the speed/power wall. Then
of course you can try to push that by making the machine wider.
The process does the lather, rinse and repeat with new process
slipping in to help out but we are approaching the sub atomic
level were transistors perform badly as there are not enough
molecules in them! So we go back and add more parallel cpus
on the same die and that means more transistors and we go
around again.
Allison