11 Aug
2006
11 Aug
'06
1:03 p.m.
Wodelf explicitly implied
PS... Upgrade now to 12/24 bits forget your old 8080
and get with the latest
in 70's technology.
Why mess with the low-end mini stuff? Build something with style, power, and 36-bits.
Or, be unconventional and do 37 or some other prime number.
11 Aug
11 Aug
1:25 p.m.
Scott Quinn wrote:
Wodelf explicitly implied
Why mess with the low-end mini stuff? Build something with style, power, and 36-bits.
Mosty because I want to keep it simple. One PCB for the control logic and
two PCBS's for the DATA PATH. That leaves using 4 bit slice chips a 24/32/40
bit word length. 24 bits keeps it in the small computer - large process controler
rather than a main frame style of computer.
Or, be unconventional and do 37 or some other prime
number.
I'd like to do '42' but that number was already taken by the SI-FI guys.
I still would like someday to build a trinary computer -1,0,+1 as a real
system.
1:35 p.m.
On 8/11/2006 at 11:25 AM woodelf wrote:
How about being really unconventional and building an asynchronous CPU?
Cheers,
Chuck
Or, be
unconventional and do 37 or some other prime number.
I'd like to do '42' but that number was already taken by the SI-FI guys.
I still would like someday to build a trinary computer -1,0,+1 as a real
system.
1:53 p.m.
Chuck Guzis wrote:
How about being really unconventional and building an asynchronous CPU?
The only design I like is this one - 40 bits wide, but it is unfinished.
http://www.hanssummers.com/index.htm
Cheers,
Chuck
2:08 p.m.
Chuck Guzis wrote:
On 8/11/2006 at 11:25 AM woodelf wrote:
How about being really unconventional and building an asynchronous CPU?
Didn't SDS make something like that?
Or, be
unconventional and do 37 or some other prime number.
I'd like to do
'42' but that number was already taken by the SI-FI guys.
I still would like someday to build a trinary computer -1,0,+1 as a real
system. 
3:58 p.m.
New subject: async designs (was Re: Group buy for homebrew CPU)
Chuck Guzis wrote:
At one time async logic was a hot topic.
The IAS machine (von Neumann/late 1940s) is listed in various places (under
'clock rate') as being 'async'. (And - annoyingly - those listings then
don't
provide an effective instruction rate for the sake of comparison).
I've been curious as to more precisely how the timing was accomplished in that
(those) machines. Offhand, I suspect you still end up with delay elements in
the design at various points to ensure some group (worst case) of signals/paths
are all ready/stable at some point and you end with a more-or-less 'effective
clock rate' anyways and don't gain much.
Such all started with ENIAC didn't it?, which - based on what I've been able
to find/read - could be described as an async design.
Was async still being discussed in the 60's?
4:13 p.m.
New subject: async designs (was Re: Group buy for homebrew CPU)
On 8/11/2006 at 12:58 PM Brent Hilpert wrote:
Such all started with ENIAC didn't it?, which -
based on what I've been
able to find/read - could be described as an async design.
Was async still being discussed in the 60's?
I think it's never really gone away. There may still be some multiplier
chips kicking around that have a "done" flag. In theory, async affords the
lowest power consumption and the highest speed, since things change state
only when required to do so by the data flowing through them, instead of
everytime the clock changes state. The gotcha is that the synchronizing
logic takes up its own power.
4:53 p.m.
New subject: async designs (was Re: Group buy for homebrew CPU)
Chuck Guzis wrote:
On 8/11/2006 at 12:58 PM Brent Hilpert wrote:
And the fact that synchronizers don't (synchronize, that is :> )
Such all started with ENIAC didn't it?, which
- based on what I've been
able to find/read - could be described as an async design.
Was async still being discussed in the 60's?
I think it's never really gone away. There may still be some multiplier
chips kicking around that have a "done" flag. In theory, async affords the
lowest power consumption and the highest speed, since things change state
only when required to do so by the data flowing through them, instead of
everytime the clock changes state. The gotcha is that the synchronizing
logic takes up its own power. 
7:08 p.m.
New subject: async designs (was Re: Group buy for homebrew CPU)
I've been curious as to more precisely how the
timing was accomplished in that
(those) machines. Offhand, I suspect you still end up with delay elements in
the design at various points to ensure some group (worst case) of signals/paths
are all ready/stable at some point and you end with a more-or-less 'effective
clock rate' anyways and don't gain much.
Such all started with ENIAC didn't it?, which - based on what I've been able
to find/read - could be described as an async design.
Was async still being discussed in the 60's?
The first PDP-10 (KA-10) processor is complete async. It also seems to
me that the PDP-9 processor is syncronous, but its clock cycle is
derived from a bunch of one shots that kick each other in a circle, in
a very async fashion. At least that is what I was told by the RICM
guys.
--
Will
1:31 p.m.
Scott Quinn wrote:
Wodelf explicitly implied
Or some weird Harvard architecture with radically different code/data
sizes. Use prime numbers for both. 8-)
Peace... Sridhar
PS... Upgrade now to 12/24 bits forget your old
8080 and get with the latest
in 70's technology.
Why mess with the low-end mini stuff? Build something with style, power, and 36-bits.
Or, be unconventional and do 37 or some other prime number.
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11 comments
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