On 2017-Mar-30, at 1:13 PM, Noel Chiappa via cctalk wrote:
FYI this is the same problem designers hit with
DRAMS back 40 years ago.
This didn't ring (pun not intended) a bell for me; can you say a bit more?
From: Chuck Guzis
I'll offer a suggestion that if your SD card
*must* be a significant
distance from its host
Like I said, this is a pre-prototype; on the production units, there will be
_no_ cable. The SD socket will be about 1-2" from the FPGA.
From: Dwight Kelvey
this behavior on my PDP-8/e where a 7474 flip
flop chip was bad. The
input looked great and the output was "half baked"
There's no chip at all on the driving end of the line (just that 470K
resistor); we see this with the SD card _unplugged_. And we see the exact
same thing on several lines.
I'm still not clear, from the discussion, how exactly that nice
interference is happening - could it be capacitative crosstalk? (I'd have
thought capacitative cross-talk would be inverted - driving a positive voltage
on one 'side' of the 'capacitor' would, I would think, induce an
voltage on the other. But I'm clearly no EE! :-)
I don't have a full enough picture of the circuit and circumstances to provide a
definitive suggestion but, some principles:
Yes, you can 'pass' a square wave through a capacitor - if you couldn't then
all the theory behind capacitor-coupled audio amplifiers would be shot.
The condition required to do so is a long resistor - capacitor time constant relative to
the period of the (square) wave:
RC time constant: t(seconds) = R (ohms) * C (farads)
With a high load R, and large enough C, the current in an R-C series circuit is limited to
a tiny level, so it takes a long time for the cap to fully charge.
For as long as the cap is charging there is current flowing through the R and so you see a
voltage drop across the R.
If you reduce the R value or the C value, at some point you would see the square wave
start to distort (the flat top would start to slope down to the right / later in time),
as the capacitor would start to reach full charge within the period of the square wave and
the voltage would start to divide between the C and R.
No, you won't see the inverse polarity, if you drive a + voltage to one side of the
cap it sucks the electrons out of the plate on that side, that attracts electrons into the
other 'load-side' plate. Those electrons are coming from (being drawn away from)
the rest of the load side circuit, here through the R, so you see a + voltage across the R
(current is flowing from GND through R into the C, so the RC-junction side of R is more +
than the GND side of the R).
It's not clear C-coupling is what's going on here (the wave shape looks pretty
sharp for what I understand of the circuit/layout).
Notably though, C-coupling would remove any DC bias, but David's screen shot indicates
a DC bias on the line.
Is this line currently connected to the FPGA, or is it just the wire and R?
Perhaps the bias is coming from the FPGA, with C-coupling of the wave via the wire.
Or perhaps it's all crosstalk from within the FPGA, 'visible' because of the
high load R.
If the wire and FPGA pin are connected, separate them (reduce the wire circuit to just the
wire and R to GND): see whether the DC bias and/or the square wave disappear.
You could play with reducing the load R value to see what happens to the sig level and
(You've mentioned both 470K and 270K for the R, could make a difference to the