Hello all together, i restore a rk05 disk drive in combination with an Plessey RK8E clone controller. Now the drive itself is restored, and the connection cables are built. My problem is that the rk8e diskless controll test (dhrka) fails with an data break error. The diskless controlltest is running throug all register and also the databuffer test. But in the first data break routine it fails. Then i toggled in the Example program from the maintanence vol.III, Single Cycle Data Break Transfers (Write than Read). With this program the content of the SwitchRegister is written through the data buffer registers and read back to the memory. Afterwards it is compared to the original SR content. I found out that the routine is running if SR=7777. Deeper investigation results that the bits 0, 1, 4, 6 and 9 have to be one`s to run the routine. The other SR bits are switchable while running the program. Next thing i did is trying read data with futil. i could read data form the disk. But with many read errors. Because i do not know anything about the allignment between my diskpack and the drive, i formated the pack with the RK8E Formater (dhrkd). The write part of the format is running. In the disk checking part the formater fails. Anyway. Then i used futil and scanned the whole surface off the diskpack. On the whole disk are 5 bad blocks left. Now i am able to dump blocks from the disk. But it seems that no matter witch block i dump out, it is the same block all over the disk. Afterwards i tried to modifie some words in block 0. And this is working. When i write the modified block i see the modification also in every other block of the disk. Have anyone the lightning idea? On a Google search i found a post of Rick Bensene from 2014 on this list witch described a similiar problem. In this discussion where talked about an spike in the load signal of the current address register. I checked that and see that this was not my problem. Thanks in advance Marco Rauhut