Hi All,
I'm thinking of building a "somewhat vintage" two-channel DAC board,
intended to drive an oscilloscope as a vector display. I'm just considering
parts now, unless someone has a really good design already set to build.
By "somewhat vintage" what I mean is that I don't want to just drop in
a modern "super chip" that will have ten (or more) times the power of the
intended host computer which, by the way, is an SWTPc 6800. I figure the
board will have some 8-bit processor on it. I'm leaning towards a Z-80.
It will have an EPROM, some scratch static RAM, some glue logic to manage
the communication with the SS-30 bus... and this is where I get fuzzy... a
1Kx8 dual ported static RAM and two DACs. These last two elements (the
dual ported SRAM and the DACs) are where I don't have any experience. A
little googling has led me to the IDT7130 for the dual ported SRAM and the
DAC0830 for the DACs. Does anybody in cctalk land have experience with
either or both of these chips? I have a source for the DAC0830, but I don't
have a source for the IDT7130 yet. The basic idea of the design is for the
6800 to write a vertex list into the dual ported SRAM which the Z-80 then
reads and pushes to the DACs. I'm hoping I can just hang these chips off of
the Z-80 address and data busses like the RAM and EPROM but I need to do
some more reading of the spec sheets.
Any help greatly appreciated,
OK, some thoughts...
You first need to decide how you're going to produce the vectors It's
obviously importnat that not only do the 2 DAC output voltages get to the
right values (that is, the vector ends i nthe right place), but also that
they get there along a 'straight line' from where they were. There are 2
basic ways of doing this, the older one (which has a lower transistor
count, but is a right pain to get working) is to do it in the analogue
circuirty, that is the DACs 'jump' to the new valuse, the analogue
circuitry then genreates the appropariate ramnps to mvoe the beam), the
other is to do it digitally, calcualting stairsteps along the vector,
moving the DAC ouptus one step at a time, and using analogue circuitry to
smooth the result.
Unless there are good reasons not to, I would recomend the latter
approach.
You can porduce the stairsteps eitehr using simple logic ICs (take a look
at things like the DEC VT11 system) or using a microprocessor. The latter
is probably easier. Jaut about any processor would be fine, I see no
reason not to use a Z80
Somethign to be acaefule of is the relative speed of drawing differnt
length vectotrs. If the beam moves more slowly on some lines than on
otehrs, the former will appaer brighter on the screen.Try to keep drawing
speed constant.
There are then 2 other parts to the project. The first is the DACs
themselves. I think you want more than 8 birs of resulution -- 12 bits
would seem to be sensibe (12 bit DACs are not that expensive now). Try to
get double-buffered DACs, which allow you to load the input regsters from
the processor and then later transfer that registers's contents to the
DAC iteself. The advantage of that is the processor can output the 4 values
(high and low parts of X and Y) and then update both dacs simultaneously.
Without that, you might get little glitches on the display.
The otehr part is communication to the host. You have suggested dual-port
RAM, which is certianly oen way to do it. I would suggest looking at FIFO
buffers (each side cna write to a FIFO which si read by the other side.
Of even just a pair of ports with handshake flags. SOemthing like this :
'374
-----------
8 | | 8
Data Bus 1 ---/------| D Q |--------/--------Data Bus 2
| |
| Clk OE |
-----------
| o
WrStb/------+--------+ |
| +--+-----------+----RdStb/
| | |
| o |
| --------- +--|\
| | R | | >o---- Ready Flag
| +5V--|D Q|o-----------|/
| | | '00
+-------|> |
| |
---------
E.g part of '74
The ready flag shoud lbe readable by an input port on each processor. The
ideea is the processor 1 can write to the '374 latch, when it does so, it
sets the D-type at the bottom, maingign the ready flag line go high.
Processor 2 can detect this, it will then read from the '374, clearing
the D-type and briinging the ready flag low again. Processor 1 can
monitor the flag line too to see when processor 2 has read the data. The
NAND means that the ready flag will remain high while proecessor 2 is
reading (and thus asserting the reset line to the D-type) so proecessor 1
doesn't try to writ at this thime (when it couldn't set the D-type).
Take a look at the hP120 schematics to see how a pair of Z80z can
communicate using this sort of circuitry.
-tony