Hello, everyone, I am happy to report, at least so far, my RK8E/RK05 are working well after applying the hardware patch to the RK8E that was suggested by David Humphries, who had a similar issue some time back, and engineered this fix. I have successfully formatted a known good pack, ZEROed the directory structure on RKA0: and RKB0:, and was able to do a DIRect on both filesystems and they came back with no errors. I was then able to successfully copy RXA0: (my boot RX01 floppy) to both RKA0: and RKB0: with no problems. I then deleted everything on RKB0: and did a SQUISH on it, and it was all good. I am able to create new files, I ran a PAL assembly of the DHRKAE (Diskless RK8E Controller Diagnostic), with the source, binary, and listing directed to RKB0:, and everything sailed through with no problems. I have the oscilloscope hooked up to the CLK, LOAD, and LSB of the Current Address Counter, and the transient that was on the CLK line is GONE. Right now the system is running the RK8E Confidence Test (which takes quite a while). So far, so good. Before I document the hardware patch, a word of warning -- there are quite a few different versions of the RK8E, as well as a lot of different ECO's (Engineering Change Orders) that were made to the board set over time. Some of the ECOs were related to trying to fix this known timing issue in some PDP 8/e/f/m systems. The fix may not work in all cases. Be aware of the revision level of your RK8E -- you may have to adapt the fix if your RK8E is showing this issue. I strongly advise scoping the Current Address Counter CLK and LOAD lines to verify that your system is having the spike on the CLK line before trying the fix. Also, I take no responsibility for anything that happens to you, your RK8E, your PDP 8, or your RK05 drive, nor do I take any responsibility for this fix working in your system. You are on your own. My RK8E appears to be at revision level B for the board set, and it has a number of ECO wiring on both the M7104 and M7105 boards. The M7106 board is virgin, with no ECO wiring. The issue is caused by a timing relationship between the IOT decoder that generates a strobe when the DLCA (Load Current Address Counter) instruction is decoded, and the system TP3 timing signal generated by the CPU. Depending on the timing of these two signals, a transient can be generated on a clock line for the string of three 74161 synchronous binary counters that make up the Current Address Counter. This transient can cause the Current Address Counter to erroneously increment after it is loaded with an address, resulting in a drive system that flat doesn't work. Every disk transfer is "off by one" in terms of where the data from the drive is transferred into or out of memory via single-cycle data break (DMA) cycles. The fix that David suggested is quite simple. It involves piggybacking on a 7474 TTL Dual D Edge-Triggered flip flop to the M7105 board of the RK8E, adding three patch wires, and cutting one trace. I modified the patch a little to make the wiring easier for me. My hands are kind of shaky, and it takes some real patience to do this kind of stuff. You will need to refer to the RK8E printset for your version of RK8E to identify where the chips are and how this patch fits into the logic. - First, you need to find a good TTL 7474 chip. Don't use LS or S, or other types, just a plain 7474. - Bend all of the leads EXCEPT pin 7 and pin 14 (GND and VCC) so that they are 90 degrees away (outward) from the package. - Piggy back the 7474 chip on top of the chip at E40. David's patch involved doing this on E41 rather than E40, but I find the wiring easier to do with the 7474 piggyback on E40. - Solder pins 7(GND) and 14(VCC) so they connect to the pins on the E40 package. This provides power to the 7474 chip. - Using appropriate wire, connect the D(pin 2) and CLR(pin 1) inputs of the 7474 to E41 pin 10. - Connect the CK(pin 3) input of the 7474 to E41 pin 9. - Cut the trace that connects E41 pin 10 to E28 pin 12 - Connect the Q output(pin 5) of the 7474 to E28 pin 12. Triple check all your work before trying it out in your system. That's it. With this patch in place, the TP3 pulse is latched by the 7474, which prevents it from going low (thereby generating the false clock signal) before the DLCA instruction is completed. My sincere thanks to all that wrote to me or posted here regarding my adventure in RK8E land, and special thanks to David Humphries for noticing my original posting sounding familiar, and writing to me about his adventure. This mailing list never ceases to amaze me with the talents that are out there. Best wishes to everyone, Rick Bensene