Gene Buckle wrote: CHEAP ! -- Ben Franchuk --- Pre-historic Cpu's -- www.jetnet.ab.ca/users/bfranchuk/index.html

Horsefeathers! The reason they did all the stupid stuff they (IBM) did was because INTEL told them to, since there was nobody on the PC team smart enough to design a microcomputer, yet dumb enough to risk doing it in their (IBM's) corporate environment. ISTR that the original cause for the presence of the 8255 was the need for it in the parallel port (see the comments in the original BIOS listings in the tech ref). The 8250 was a fine chip for the application, though I wonder why they used the DIP version. There were better choices available, but they didn't want to lose the serial port board business by putting two of them on the same card, and by that time serial I/O chips tended to have between 2 and 8 ports on them. Dick ----- Original Message ----- From: "Peter C. Wallace" <pcw(a)mesanet.com> To: <classiccmp(a)classiccmp.org> Sent: Friday, December 14, 2001 12:28 PM Subject: Re: MITS 2SIO serial chip?

----- Original Message ----- From: "Peter C. Wallace" <pcw(a)mesanet.com> To: <classiccmp(a)classiccmp.org> Sent: Friday, December 14, 2001 2:19 PM Subject: Re: MITS 2SIO serial chip? enough original Nobody, including the dumbest at IBM, was dumb enough to use the high-level, positive edge-triggered interrupt without pressure from Intel. Apparently Intel had ONE guy at some time in history who devised that ridiculously stupid approach to interrupt processing and built it into their "scheme" which was followed by a series of devices that lived on that scheme. Once they had it, they were stuck with it. the PLCC-44 by dual: Signetics 2681/68681, Z80 DART would have worked fine too, with the exception that the Intel bus didn't work with the "mode-2" interrupt, which you weren't require to use; octal: TCM78808 which looked pretty much like 8 2661's. I didn't like the package.

<snipMy old TI datasheets are hiding, so I can't verify what was when. I'm not sure exactly what difference it makes whose bus the serial I/O chip is designed for when the whole bunch of devices use essentially the same signals to get the job done. The DART doesn't work much differently than any other serial I/O device so long as you don't attempt to use some of its unique features. It seems to me that it takes about the same quantity of machinations to make the 8250, which is also not ideally suited to the ISA bus, work on the ISA bus, as it would take to make a Z80 DART or an 8251 or a 2651 do the job. Likewise for the 2681/68681. No matter what you need, a small PAL will do the trick. That certainly wasn't lost on I/O board makers. I checked the actual board, and the PLCC part that I designed in to the board I was thinking about. It turns out the early version used a few 68-pin PLCC sockets, and, in fact, there were no 44-pin PLCC's on that board. The part in the PLCC socket, BTW was not a PLCC, but a JEDEC 'C' package. Though there was paper for the PLCC, the only parts used on the prototype board in that application were in the JEDEC 'C' package. Fortunately, unlike the JEDEC 'A' package, (that leadless single-sided ceramic chip carrier in which i80186's and i80286's were commonly used) the 'C' package would easily work in a PLCC socket. A later version, however, did, indeed have the 8250's in the PLCC-44 on it. I really don't think practical considerations such as cost entered into the early decision stream in the PC development, once it reached the point at which upper management was prepared to pull the plug if at least one milestone wasn't met. The way I heard the story from some of the guys who worked at Boca was that there wouldn't have been an IBM PC if Intel hadn't presented the guys with a board-level prototype of the '188 (not an application of the '188). While it's easy enough to believe that the entire project had deteriorated into a "Chinese fire drill," I can't believe that Intel would have had the brains to present a canned solution to them in time to pull the chestnuts from the fire. Dick > > > > ----- Original Message ----- > > > > From: "Peter C. Wallace" &lt;pcw(a)mesanet.com> > > > To: &lt;classiccmp(a)classiccmp.org> > > > Sent: Friday, December 14, 2001 12:28 PM > > > > Subject: Re: MITS 2SIO serial chip? > > > > > > > > > > > On Fri, 14 Dec 2001, Gene Buckle wrote: > > > > > > > > > > > NS* did use them as did many others. The worst chip was > > > > > > > the 8250. > > > > > > > > > > > Which makes me wonder what possessed IBM to pick it for the PC. > > > > > > > > > > > g. > > > > > > > > > The same reason they chose active high edge triggered interrupts on the > > > > > bus (wrong on both counts) > > > > > > > > > The same reason they used 8 bits of an 8255 to read the KB shift register > > > > > that had a (unused) tri-state > > > > > > > > > The PC = A horrible, amateurishly designed kluge > > > > > > > > > > > > > Peter Wallace > > > > > > > > > > > > > > > > > > > Peter Wallace > > > Mesa Electronics > > > > > > > Peter Wallace > Mesa Electronics

I don't think the DART would have been such a mess. If you AND (/IOR and /IOW) you get a useable IORQ, not that you really need it, since it's only used in conjunction with M1 to signal the mode-2 interrupt acknowledge, which wouldn't occur in this case. If the device is selected I'm not at all sure it cares one iota whether IORQ is active. see below, plz. Dick ----- Original Message ----- From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Friday, December 14, 2001 6:45 PM Subject: Re: MITS 2SIO serial chip? is signals to serial It the as for That Not exactly direct. you do have to invert the ALE to form the DataStrobe or whatever that signal was. I always liked the 8250 because it was a 1-part solution to a problem otherwise using two or more parts. It is a convenient part for the ISA, but since the ISA presents all the other signals, /IOR, /IOW, etc, from which you can derive the required signals in a 16L8 anyway, which is what most of them used for decoding the addresses, you could make whatever signals you needed. board I in was 'A' and socket. which wasn't with to fire. on

Well, that doesn't change the fact that if you AND /IOR with /IOW you get a useable /IORQ. Whether you feed the /IOW forward doesn't matter. I stand corrected on my presumption that the M1 and IORQ were used solely for the int handshake. I never liked the Z80 peripherals and never even once used one in my own work, though they were everywher in commercial hardware. Even my HP plotter has one it it, though it doesn't have a Z80. I believe the reason they were so widespread in their application was that the Zilog and Mostek application notes seemed, unlike those from Intel and MOT, to work without any additional effort, so anybody could copy one and use it, to wit, the Ferguson Big Board, and Big Board II, among others just like it. The reason I didn't like 'em, BTW was because the peripherals limited the rate at which you could run your system without major effort, unless you didn't mind giving up the features for which you'd bought them. Dick ----- Original Message ----- From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Saturday, December 15, 2001 8:38 AM Subject: Re: MITS 2SIO serial chip? /IOW) wouldn't one chip features. make bus, Likewise /IOW, is PLCC part there JEDEC i80186's it. the at was guys While into a brains PC. interrupts shift

That's what clocks are for. As I wrote before, you derive the /IORQ from the /IOR and /IOW, build your select from those as well, and then use a registered output for the /RD signal. The default bus clock is 8 MHz, and the default for the -A SIO/DART is 4. That should provide enough setup time. Dick ----- Original Message ----- From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Saturday, December 15, 2001 10:33 AM Subject: Re: MITS 2SIO serial chip? for used my Well ... we digress ... I never liked the Z-80 setup because the peripherals basically limited the CPU speed, and I liked the Z8000 series even less, though I don't remember why. I didn't EVER use an Intel product (other than at the board level) until the 80186 came out, BTW. <snip> > > Dick > > ----- Original Message ----- > > From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; > > To: &lt;classiccmp(a)classiccmp.org&gt; > > Sent: Saturday, December 15, 2001 8:38 AM > > Subject: Re: MITS 2SIO serial chip? > > > On Fri, 14 Dec 2001, Richard Erlacher wrote: > > > > > I don't think the DART would have been such a mess. If you AND (/IOR and used in cares > > one > > > > iota whether IORQ is active. > > > > Not true, the DART like the SIO has no write signal... > > > > > > > see below, plz. > > > > > > Dick > > > > ----- Original Message ----- > > > > From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; > > > > To: &lt;classiccmp(a)classiccmp.org&gt; > > > > Sent: Friday, December 14, 2001 6:45 PM > > > > Subject: Re: MITS 2SIO serial chip? > > > > > > > > > On Fri, 14 Dec 2001, Richard Erlacher wrote: > > > > > > > > > <snip> > > > > > > > Dart is Z80 bus, (like an Async only SIO) not Intel. Have to take your > > > > > > > word on the TCM78808 - sure it was available in 1981? > > > > > > > > > > > My old TI datasheets are hiding, so I can't verify what was when. > > > > > > > > > > I'm not sure exactly what difference it makes whose bus the serial I/O same other ISA trick. > > > > That > > > > > > certainly wasn't lost on I/O board makers. > > > > > > > > > > > The 8250 is a direct ISA bus interface (no logic other than decode needed) that > > > > > there's anything wrong with the Z80 way) > > > > > > > Not exactly direct. you do have to invert the ALE to form the DataStrobe or 1-part convenient /IOR, which whatever > > > > signals you needed. > > > > Yes exactly direct! There is only decode and direct connection from IOW to > > > input data strobe and IOR to ouput data strobe. Take a look at the Asyc > > > card schematic in the XT tech ref. ALE is not needed for I/O on the ISA > > > bus, only for latching the LA bus (which is above the 64K limit of I/O). > > > > > > > > > > > > > > I checked the actual board, and the PLCC part that I designed in to the 68-pin The Though that PLCC on > > it. > > > > > > > > Sure, there are 8250's (and 16450's and 16550's etc etc) in PLCCs, just > > > > > not in 1981... > > > > > > > > > > > > > > I really don't think practical considerations such as cost entered into point milestone Boca the '188). the > > > > fire. > > > > > > > > > > Dick > > > > > > > > > > > > > > ----- Original Message ----- > > > > > > > > > > From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; > > > > > > > > > > To: &lt;classiccmp(a)classiccmp.org&gt; > > > > > > > > > > Sent: Friday, December 14, 2001 12:28 PM > > > > > > > > > > Subject: Re: MITS 2SIO serial chip? > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, 14 Dec 2001, Gene Buckle wrote: > > > > > > > > > > > > > > > > > > > > > > NS* did use them as did many others. The worst chip was > > > > > > > > > > > > > the 8250. > > > > > > > > > > > > > > > > > > > > > > Which makes me wonder what possessed IBM to pick it for the > > PC. > > > > > > > > > > > > > > > > > > > > > > g. > > > > > > > > > > > > > > > > > > > > The same reason they chose active high edge triggered > > interrupts > > > > on > > > > > > the > > > > > > > > > > > bus (wrong on both counts) > > > > > > > > > > > > > > > > > > > > The same reason they used 8 bits of an 8255 to read the KB > > shift > > > > > > register > > > > > > > > > > > that had a (unused) tri-state > > > > > > > > > > > > > > > > > > > > The PC = A horrible, amateurishly designed kluge > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Peter Wallace > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Peter Wallace > > > > > > > > > Mesa Electronics > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Peter Wallace > > > > > > > Mesa Electronics > > > > > > > > > > > > > > > > > > > > > > > > > > Peter Wallace > > > > > Mesa Electronics > > > > > > > > > > > > > > Peter Wallace > > > Mesa Electronics > > > > Peter Wallace > Mesa Electronics > >

I disagree that it's a mess. I haven't looked at the requirements for a Z80 peripheral since the early '80's, but I can assure you that I'd dispose of any 1st year engineering intern who couldn't whip up a suitable PAL or equivalent MSI/SSI logic to handle the generation of properly timed inputs to the thing in an hour or less. See below, plz. regards, Dick ----- Original Message ----- From: "Peter C. Wallace" &lt;pcw(a)mesanet.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Saturday, December 15, 2001 9:03 PM Subject: Re: MITS 2SIO serial chip? the registered for My point was that, with a PAL, you can decide what timing you want and produce it from the ISA signalling protocol, regardless of the specifics. It's not rocket science. The presence of either /IOW or /IOR tells you there's an IO cycle in progress. If you register that negative logic NOR (the equivalent of a 2 input NAND, in this case) you can then register the output and feed that forward to create the required strobes in whatever order you see fit. Writing the equations, compiling them, and programming the PAL should take no more than 5 minutes. That's a lot less time than figuring out what you can do with unused SSI components already on the board, if there are any, so, from that standpoint, it's just economics. It's no accident that the select and enable timing to the 8250 on most I/O boards was also done with a PAL get a solely once Even though (/IOR which it take when. serial any unique machinations to the job. the (not anyway, IOW to Asyc ISA I/O). to board. in the which in a PLCC-44 entered at presented deteriorated the from chip for the KB

"Peter C. Wallace" wrote: I never heard about pal's until about 1990. In some ways the peripheral chips are in a really sorry shape. You have vintage slow I/O (2 MHZ?) or PC motherboard chip sets. Nothing in between. On my FPGA I can run with a 250 ns memory cycle, but need to stretch it to 625 ns for I/O. -- Ben Franchuk --- Pre-historic Cpu's -- www.jetnet.ab.ca/users/bfranchuk/index.html

On Sun, 16 Dec 2001, Ben Franchuk wrote: PALs were certainly available earlier, just expensive, non-reprogramable, and power hungry. I think we used our first programmable logic in 1986 (Altera EP900s and EP320s - both low power) for emulation of some PC motherboard stuff in our low power V40 based embedded PCs. We never used PALs but have used GALs a lot for simple decoders and random logic. At about $.50 now they are hard to beat. I think I would do most non-common (probably not Ethernet, USB or video) I/O these days with FPGAs. Its great to be able to change the function and pinout with just a downloadble config file. A 100K (Well maybe 15K if you remove Xilinx inflation factor) SpartanII chip is only $19.00... Peter Wallace Mesa Electronics

On Sun, 16 Dec 2001, Richard Erlacher wrote: I think you are missing the point, In 1981 PALS were expensive... As far as the EPXXX Parts go, I was just mentioning when we first used programmable logic. We made low power systems so we had to wait until CMOS parts were available at a reasonable price. When we started using Altera, there was no second source, Intel parts were available only a few years later, and TI after that (and only a few parts) Not quite, you need to generate a wait state so IORQ is more than 200 nS long (since we lost a cycle generating the RD --> IORQ delay), so you need a tri-state output to drive IOCHRDY, and theres that niggling timing question with the DART's clock signal. Maybe it would work with the ISA clock, maybe not... I think you underestimate how tightly integrated the Z80 peripherals are with Z80 bus timing... Unless you have a compelling need to integrate the MAC part of Ethernet into a FPGA, FPGA Ethernet is more expensive than an external Ethernet chip. Also, It is not possible to integrate the PHY into a FPGA at the moment (well maybe with some oddball mixed signal part) and when I can get a 100BT Ethernet chip with integrated PHY for less than $5.00, it would be silly to use a major portion of a $20 chip for a non standard Ethernet interface that doesn't even have any driver support... Peter Wallace Mesa Electronics

On Mon, 17 Dec 2001, Richard Erlacher wrote: I am perfectly aware of multiple channel serial chips, we used one in our Sprite CPM machine in 1978... And its not just that I dont like the DART in a ISA environment, I dont think it even makes sense to use it as you suggested. I doubt that there is a single add-on card that uses a DART for the ISA bus... and, while I think it's at Takes much less logic, only a decode Just because YOU don't like I pressume thats why IBM chose it since it supported a full set of Modem control lines... Peter Wallace Mesa Electronics

Wrong! The ISA bus is not multiplexed (well for I/O anyway) the 8250 adress strobe is simple grounded and you have to deal with the Wrong! Easily met with 4.77 or 8 Mhz bus speed which the bus doesn't. ... pretty much the same as 8250 meets the bus specs no problem... Peter Wallace Mesa Electronics

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I don't know what "WORST" means in this context, but I never had a bit of trouble with the 8250, having used it in a number of mass-produced applications. A lot depends on your expectations and on how well you've read the datasheet. If you built the hardware to work with the device you've designed in, following the spec's, they all worked pretty well. The old UARTs were, far and away, IMHO, the easiest and most forgiving, though. They required the most external logic, though, and once the more intgrated chips, e.g. the 6850 with its integrated handshaking and interrupt logic, and the 8250, with its integrated that logic plus the internal baud rate generator, came down somewhat in price, the more highly integrated parts became more popular. Dick ----- Original Message ----- From: "Gene Buckle" &lt;geneb(a)deltasoft.com&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Friday, December 14, 2001 12:42 PM Subject: Re: MITS 2SIO serial chip?