Well... the QBUS does have those shared address/data lines, so its 'raw' count (i.e. number of wired-or broadcast bus lines) is somewhat lower (-16 data pins, but +4 address lines, plus various other differences). Depending on the details that may, or may not, translate into a lower pin count to the FPGA. E.g. if one has separate input and output pins for address/data lines (one needs all 4 functions for doing both incoming slave mode, and DMA), it can add up. So, I noticed that on some QBUS cards DEC used a quad transceiver with tri-state output (on the card side), the AM2908PC. It has separate tri-state drive enable, and bus drive enable, pins. The FPGA we were looking at supports bi-directional pins (i.e. tri-state output, plus input), so I conceived the hack of tying the transceiver's input and output pins together, and routing them into bi-directional pins on the FPGA. As long as one doesn't turn on the tri-state drive and the QBUS drive enable at the same time (forming a feedback loop at the transceiver chip), it _should_ work OK. (Mandatory observation about theory and practise included at this point...) So that reduces the number of pins needed by half. (Although I guess one could pull the same hack with the UNIBUS, _iff_ the 2908 can work as a UNIBUS transceiver; analog electrically, the two seem to be pretty identical.) One can further observe that on the QBUS, A and D are shared, so one doesn't need separate A and D pins. One cannot do that with the UNIBUS, since they way DATO works, the A and D lines have to be driven at the same time (with different values, of course). Noel