Yes, good example. I do not think adding some sort of -8 powered channel stuff to the KA would have disrupted things much at all - there just was not a huge number of PDP-6 installations to disrupt. Likewise, they could have included backwards compatibility. William Donzelli aw288 at osfn.org

Bob> Speaking of the CDC and its PPU's... Bob> Does anyone have software to use on the 6600 emulator? Tom Hunter's DtCyber includes a copy of COS. There is lots of other stuff but there are still restrictions on distribution, unfortunately. Also check out www.cyber1.org. Bob> Has anyone put one of these machines onto VLSI? You mean recently? I believe the University of Illinois did that in the late 1970s, or at least was thinking about it. I've seen some discussion recently that you could put a complete 6600 into a high end FPGA. That would be neat. I haven't heard of that being actually done, though. paul

On Thu, 16 Jun 2005 05:53:53 +0100 "Andy Holt" <andyh at andyh-rayleigh.freeserve.co.uk> wrote: [CDC6600 in a FPGA] I don't know how many gates, but the Book "Design of a Computer CDC6600" states on page 20: "the entire 6600 Computer contains approximately 400,000 transistors". It used "Direct-Coupled Transistor Logic" so there where way less then 400,000 gates. -- tsch??, Jochen Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/

Andy> As the 6600 was entirely built with discrete components, not Andy> chips, and yet had to be physically relatively compact, I doubt Andy> if it had much more than say 20,000-25,000 gates. Nowadays Andy> that isn't anywhere near high end of the FPGA ranges. It's quite a lot more than 20k gates. Looking at the diagrams in Thornton -- the individual logic modules are surprisingly dense. I counted 25 gates on one of the adder modules (and it's more than that if you use FPGA "gate equivalents" since many of them had more than 2 inputs). He also says that each chassiss can hold 756 logic modules (18 rows at 42 modules per row). And there are 7 logic chassis in a 6600 (8 more are memory, one is unused). So if an average module is 20 gates that gives 100k gates. Cray always was much better at densely packed logic than everyone else. Check out Thornton's book (it's on bitsavers). Chapter 3 nicely shows the packaging and how it gets so much stuff in so little space. Lastly, the conversion I was reporting involved putting the central memory on-chip too; without that, you'd either lose a lot of performance or use up a whole lot of pins for wide memory. paul

Indeed ... weren't the 10 PPUs multiplexed through one arithmetic unit - a FPGA implementation would almost certainly find it simpler to have 10 non-multiplexed identical units (would up the gate count but simplify almost everything else). Andy