Logic testing - test-drb@ccmp.vtda.org

5 Mar 2008

ard at p850ug1.demon.co.uk (Tony Duell) said:
...
   Not so useful
with peripherals though, I find a storage scope is  
 invaluable for them, the more traces the better, so I suppose a logic  
 analyser would be useful, but does one exists for MINUS 6.3 volt  
 logic? I always presumed they were only invented after silicon  
 replaced germanium and so only work with positive logic voltages.    
 I fail to see what silicon .vs. germanium has to d owith the polarity of 
 the logic cignals. In general PNP transistors, and for that matter PMOS 
 fets, imply -ve logic levels, and plenty of machines were built using 
 those components. Also ECL chips have -ve logic levels (around -2V) wrt 
 ground. 
But...
Logic levels are different when using PNP transistors.  IBM in its SMS series
cards used "S" levels (+S and -S) which were -12 and 0volts.  Commonly
germanium transistors were PNP, and the Vcc rail was a negative voltage (in the
case of SMS cards -12 volts).  If you have a logic analyzer, you can TRY to use
it by connecting the ground level reference to -12 volts and hope that
something doesn't blow because the analyzer's ground is now at -12 volts and
logic levels go "up" from there.  It usually helps to have a NEMA adapter
(ground lifter) to isolate the third prong ground on the power connector (it
has been known that some people cut off this connection).
On PMOS levels (intel 4004 was an example) they used +5 for Vdd and -9 for Vss
as I recall.  You needed pull downs to -9 on some pins to interface with TTL. 
PMOS wasn't the easiest to interface with non-PMOS stuff (but it was done).

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