8 Jul
2006
8 Jul
'06
4:33 p.m.
Subject: Re: OMTI parallel port interface hack
From: ard at p850ug1.demon.co.uk (Tony Duell)
Date: Sat, 08 Jul 2006 22:44:30 +0100 (BST)
To: cctalk at classiccmp.org
It is mentioned in the Intel 8255 data sheet.
> offhand if that's the case for other brands as well? I believe I have some
> NEC parts around somewhere.
It applies to ALL 8255s. For some uses this is not a problem, others just
plain annoying. All a side effect of putting 10# in a 5# bag if you ask me.
However of all the parallel devices it's widely available (even in CMOS)
and despite it's flaws it's still more versitile than any other PPI.
An alternate if the application can tolerate it's interface is the 8155
(22 IO lines and 8085/8088 muxed data/address interface).
The
problem is that the 8255 is fundamnetally broken as designed (well,
I'd expect that from Intel, alas). Any write to the mode control register
clears all outputs to 0's. Which means you can't reverse the direstion of
one of the 8 bit ports without mucking up everything else.
Oh really? I've never heard _that_ before about these parts... Do you know
It certainly applies to the National Semiconductor
version. I used one in
my first Z80 homebrew, and one of the first programs I wrote once I'd
added it simply configured all ports as outputs, wrote a suitable value
to port A, then jumped back to the start. I then found the lines that
should be high were, in fact, pulsing. Reading the data sheet showed why
(I was re-loading the mode control register, thus clearing the output
ports). Of course it was trivial to correct in this program, but it sure
made life difficult later.
Once you know this it's less a problem. Hint: if you invert the outputs
and add pullups you can hide the problem for some cases.
For many apps it's not a problem. The upside is 24 IO lines. Or two
ports with full handshake and interrupt posting. No so bad really.
For some cases using the 8255 is way overkill and a LS273 was more
suitable but then I'm barking at the design of others.
Allison
-tony
9 Jul
9 Jul
1:15 p.m.
It applies to ALL 8255s. For some uses this is not a
problem, others just
plain annoying. All a side effect of putting 10# in a 5# bag if you ask me.
However of all the parallel devices it's widely available (even in CMOS)
and despite it's flaws it's still more versitile than any other PPI.
I guess it depends on what you consider 'versatile' to mean, but
considering the 8255 doesn't let you individually select the direction of
each port line (the 6821, 6522 and Z80-PIO all do, I think the Z8536 does
too), considering you can't change the mode without clearing all outputs
(AFAIK no other parallel chip has that 'feature'), and considering it's
just a plain parallel port with handshakes (the 6522 contains a shift
register, counters, etc too), I think it's one of the _least_ versatile
paralell chips around.
Once you know this it's less a problem. Hint: if
you invert the outputs
and add pullups you can hide the problem for some cases.
Not really. At reset all the lines are inputs (thank %deity they got that
right, or we'd have contentions to deal with too). A TTL input connected
to one of those lines would float high (and it would be a lot easier to
pull the line high than to pull it low). After writing to the mode
register and making that line an output, it will be low. Then you write
to the port and maybe make it high again.
You either have to pull it low externally, or design your circuit to be
happy with this high-on-reset, low-after-configuration setup.
Actually, if any write to the mode register had made all outputs high it
would have been a nicer chip.
-tony
6741
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6742
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