Timing of PDP-11 Instructions - test-drb@ccmp.vtda.org

30 Nov 2005

...

Subject: Re: Timing of PDP-11 Instructions
   From: "Jerome H. Fine" <jhfinexgs2 at compsys.to>
   Date: Wed, 30 Nov 2005 21:57:37 -0500
     To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>

...
 I am still not able to figure out why the FORTRAN 77
subroutine has different timing when the destination
address is moved from PAR0 to PAR1 under RT-11 under
both E11 and a real PDP-11/73.  Cache has been suggested,
so I will attempt the calculation with a PDP-11/23
which does not have any cache.

Sincerely yours,

Jerome Fine 
Cache is half the answer. The other half is when you hit the bus
on a cache miss two things have to happen.  You have to do bus 
transactions which are very slow compared to cache and you have to
refill the cache.  IF there is any MMU action required 
(pagein/pageou) you add that overhead as well.

Remember the PDP11 is 16 bits. Any addressing outside ~28kwords
is going to involve a MMU operation.  That a lot of register 
access and it's costly(in time), more so if you need to move 
the Dmap in an I&D machine (11/73). The reason for that is those
actions lie inside the core OS and require system calls to process.
E11 is just being faithful to the core PDP11 so I'd expect similar 
if not exact same behavour.  You didn't say RTll SJ or FB.

Shame you can try that (in F77) on a VAX or PC wher 32bit address
space is the rule.  I'd expect much different behavour.. 
Till your task is paged out. ;)

Allison