A vectored interrupt is one in which the interrupting device provides part of the interrupt address. On the Z-80, this was done by the peripheral when it saw the processor's interrupt acknowledge sequence and this meant that it had to "see" both the M1 and the IORQ signals. It then reset its interrupt logic when it saw the RETI instruction being fetched. As you may have concluded, the Z-80 peripherals had to be as fast as the processor, and had to have access to the necessary processor control signals. I've never tried running a fast processor with slow peripherals and only slow the processor down to the peripheral rate when M1 or IOREQ were active. That might actually work so long as the peripheral had time to get its bus-side task finished before its next transaction came along. That might be a way to decouple the peripherals and processor. What I normally did is run the I/O cycles slowly(4 MHz), insert a wait state in the M1 cycle, and not use the Z-80 peripherals. That way I didn't have to present the M1 and IOREQ signals to each peripheral. Dick -----Original Message----- From: Arfon Gryffydd <arfonrg(a)texas.net> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Thursday, April 01, 1999 8:16 AM Subject: Re: Computer busses.... (& Z-380) What