The 8200/01/02/03 are buffer registers/arrays of 10 clocked "D" flipflops.
I have a Signetics integrated circuits 1978 data handbook, which has
them described. I will scan tomorrow (but there might be problems with
the scanner). For now, here is some data from the handbook.
The 8200/01/02/03 MSI Buffer Registers are arrays of ten clocked "D" flipflops
especially suited for parallel-in parallel-out register applications.
They are also suitable for general purpose applications as parallel-in
serial-out, serial-in parallel-out registers.
The flipflops are arranged as dual 5 arrays (8200 and 8201) and single
10 arrays with reset (8202 and 8203). The true output of each bit is made
available to the user.
The 8200 and 8201 feature true "D" inputs. The logic state presented at
these "D" inputs will appear at the Q outputs after a negative transistion
of the clock.
The 8203 and 8204 feature complementing "D" inputs ("D\"). The logic
state presented at these "D\" inputs will invert and appear at the Q
outputs after a negative going transisition of the clock. This complementing
input feature ("D\") permits the use of standard AND-OR-INVERT gates to
achieve the AND-OR function without additional gate delays.
- Henk.
________________________________
Van: cctalk-bounces at
classiccmp.org namens Vincent Slyngstad
Verzonden: di 08-05-2007 19:45
Aan: General Discussion: On-Topic and Off-Topic Posts
Onderwerp: Wanted: N8202N datasheet
Hi,
I am looking for a datasheet for the N8202N or equivalent.
It would have been described in "Digital 8000 series TTL/MSl".
It was apparently manufactured by Signetics and equivalents
seem to have been available from Motorola and others.
I have the pinout for the device. What I'm looking for is
whether the clock is edge or level sensitive, which edge or
level, and maybe something about setup and hold times, etc.
(This is to help design replacements for some hard-to-find
old DEC gear.)
Thanks!
Vince
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