The following is taken form the Intel i486 processor databook dated April 1989 (oops, sorry, it's off topic!) Intel order number 240440-001, page 164. [Interstingly it seems thet the 486 was the first whose name was prefixed with 'i' from the heading below] 11.0 Differences between the i486(tm) Microprocessor and the 386(tm) microprocessor plus 387(tm) numerics coprocessor The differences between the 4866 microprocessor and the 386 microprocessor are due to performance enhancemnets. The differences between the microprocessors are listed below. 1. Instruction clock counts have been reduced to achieve higher performance. See Secton 10. 2. The 486 microprocessor bus is significantly faster that the 386 microprocessor bus. Differences include the 1X clock, parity support, burst cycles, cacheable cycles, cache invalidate cycles and 8-bit bus support. The Hardware References and Bus Operation Sections (Sections 6 and 7) of the data sheet should be carefully read to understand the 486 microprocessor bus functionality. 3. To support the on-chip cache new bits have been added to control register 0 (CE and WT) (Section 2.1.2.1), new pins have been added to the bus (Section 6) and new bus cycle types have been aded (Section 7). The on-chip cache needs to be enabled after reset by setting the CE and WT bit in CR0. 4. The complete 387 math coprocessor instruction set and register set have been added. No I/O cycles are performed during Floating Point instructions. The instruction and data pointers are set to 0 after FINIT/FSAVE. Interrupt 9 can no longer occur, interrupt 13 occurs instead. 5. The 486 mucroprocessor supports new floating point error reporting modes to guarantee DOS compatibility. These new modes require a new bit in control register 0 (NE) (Section 2.1.2.1) and new pins (FERR# and IGNNE#) (Section 6.2.13 and 7.2.14). 6. Six new instruction have been added: Byte Swap (BSWAP) Exchange-and-Add (XADD) Compare and Exchange (CMPXCHG) Invalidate Data Cache (INVD) Write-back and Invalidate Data Cache (WBINVD) Invalidate TLB Entry (INVLPG) 7. There are two new bits defined in control register 3, the page table entries and page directory entries (PCD and PWT) (Section 4.5.2.5) 8. A new page protection feature has been added. This feature required a new bit in control register 0 (WP) (Section 2.1.2.1 and 4.5.3). 9. A new Alignment Check feature has been added. This feature required a new bit in the flags register (AC) (Section 2.1.1.3) and a new bit in control register 0 (AM) (section 2.1.2.1) 10. The replacement algorithm for the translation lookaside buffer has been changed to a pseudo least recently used algorithm like that used by the on-chip cache. See section 5.5 for a description of the algorithm. 11. Three new testability registers, TR5, TR6 and TR7, have been added for testing the on-chip cache. TLB testability has been enhanced. See section 8. 12. The prefetch queue has been increased from 16 bytes to 32 bytes. A jump always needs to execute after modifying code to guarantee correct execution of the new instruction. 13. After reset, the ID in the upper byte of the DX register is 04. The contents of the base registers including the floating point registers may be different after reset. -- Hans B. Pufal : <mailto:hansp@digiweb.com> Comprehensive Computer Catalogue : <http://www.digiweb.com/~hansp/ccc/> _-_-__-___--_-____-_--_-_-____--_---_-_---_--__--_--_--____---_--_--__--_