14 Jan
2009
14 Jan
'09
3:25 p.m.
Both Neil Franklin and
Doug Conroy have done work in this area.
Dave Conroy.
He's not had time to work on it for a while now.
14 Jan
14 Jan
3:46 p.m.
Actually, he's gotten pretty far on it. I just talked to him today
about it. I'd have to go back and look at my e-mail archives but late
Nov/Dec he had it passing all of the DEC CPU diagnostics on a verilog
simulator. Today he told me how many FFs & LUTs it took (not as much
as he thought) to implement a KA10 style CPU (so he's doing synthesis).
TTFN - Guy
On Jan 14, 2009, at 3:25 PM, Al Kossow wrote:
Both Neil
Franklin and
Doug Conroy have done work in this area.
Dave Conroy.
He's not had time to work on it for a while now.
15 Jan
15 Jan
10:25 a.m.
On Wed, Jan 14, 2009 at 6:46 PM, Guy Sotomayor <ggs at shiresoft.com> wrote:
Actually, he's gotten pretty far on it. I just
talked to him today about
it. I'd have to go back and look at my e-mail archives but late Nov/Dec he
had it passing all of the DEC CPU diagnostics on a verilog simulator. Today
he told me how many FFs & LUTs it took (not as much as he thought) to
implement a KA10 style CPU (so he's doing synthesis).
TTFN - Guy
On Jan 14, 2009, at 3:25 PM, Al Kossow wrote:
Promising! I've wanted to see a -10 in FPGA for a while now, never had
the ambition (or the hardware) to try writing one in VHDL or anything.
Good luck to Dave, I guess.
John
--
"I've tried programming Ruby on Rails, following TechCrunch in my RSS
reader, and drinking absinthe. It doesn't work. I'm going back to C,
Hunter S. Thompson, and cheap whiskey." -- Ted Dziuba
Both Neil
Franklin and
Doug Conroy have done work in this area.
Dave Conroy.
He's not had time to work on it for a while now.
5820
days inactive
5821
days old
2 comments
3 participants
participants (3)
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aek＠bitsavers.org -
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