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From: hilpert at cs.ubc.ca
dwight elvey wrote:
Hi
I have a question about micro sequences.
If I had the sequence SLA,INA
would the skip happen before the INA or
after? Would the test for the skip happen
before or after the INA?
Dwight
Micro sequence execution order is discussed in the 2100 manual
(
http://oscar.taurus.com/~jeff/2100/index.html)
in the section "3.3 REGISTER REFERENCE INSTRUCTIONS" - Alter-Skip Group (page
3-15/16).
(or for quick ref my own summary:
http://www.cs.ubc.ca/~hilpert/e/HP21xx/pgmref.html#micro)
According to the table there, the SLA is executed before the INA, so that
should answer the question of which value is tested.
Hi
This is my interpretation as well. It should test
before going to the next micro op.
I guess you could say it still leaves ambiguous or open to interpretation as to
whether the INA is skipped or not, but I would interpret the skip instructions
description "skip next instruction" as skipping the next instruction word,
rather than aborting the remainder of the micro-sequence.
That is the most interesting part. Does it abort the the micro
sequence and do the skip on the next instruction or does it
finish the micro sequence. I agree that it wouldn't be logical
to consider the micro sequence steps and instructions for the
skip.
Alternatives interpretations would be
- skip only the next micro-instruction (would require extra hardware to sort
it all out, for marginal benefit)
- skip remaining micro-instructions as well as the next instruction word
(would contradict "skip next instruction", as multiple 'instructions'
were skipped)
Skipping only the next instruction word makes sense in hardware terms as it
requires simply an extra increment of the PC.
So, in short, my understanding would be that the pre-increment value of A is
tested in the skip, but the increment is executed in either case. (I could test
it on my 2116 if necessary.)
It would be interesting to know. The manual isn't absolutely
clear on this.
I'm writing an assembler in Forth and was wondering about that.
This last weekend I inventoried my I/O boards and wrenched my
back. I'm just beginning to recover from that.
The assembler is coming along well. I've got all the instructions
coded and all I need to do now is the file I/O and adding
the macros for flow structures.
The instructions are well organized except for the CLE instruction.
One needs to know if it is in a SRG or ASG sequence before
one knows what to do. My assembler is single pass so this
required a little extra fiddling. I assume it is a SRG unless
I see the next instruction as part of a ASG.
I expect to bring my 21MX out of storage when I have some
code to run.
Thanks
Dwight
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