So, presumably in this situation the core is read out, but not written
back, under dynamic/full speed conditions.
Perhaps something interferes with the write-back portion of the cycle
under these conditions? Given that it only happens under dynamic
conditions, presumably a timing relationship issue?
That would explain why you didn't find anything wrong in the core unit
or its associated circuits.
So maybe a little test program that does something like this:
xx00 IAC
xx01 IAC
xx02 Restore IAC instruction to xx00
xx03 JMP xx00
Then trigger on the fetch of that first instruction as you look about
with the scope.
On 6/27/2012 8:05 PM, Michael Thompson wrote:
I am hoping that one of you might be able to shed some
light on a
strange behavior in the RICM PDP-8/L.
It looks like we have everything working OK except for a strange
behavior when the processor is run at full speed.
Single-stepping Instruction Test 1 works OK, so at least the processor
logic is mostly functional.
We tried just running Instruction Test 1 at full speed, but it halted at 0501.
We looked at the code in that area and found that the contents of
location 0500 was all zeros.
We loaded a little program consisting of: IAC, IAC, JMP .-2 and found
that it would replace the first IAC with zeros.
More experimenting showed that if any of the address bits 6-11 were
on, the program would work OK.
If you run the processor at full speed through an instruction at xx00,
that location is replaced with zeros.
We swapped all of the G221s, G228s, and G224s. None of the module
changes affected the strange behavior.
We swapped the M617 in slot A9, but that didn't make a difference.
The read/re-write current waveforms look OK for all addresses.
At this point we really don't know what is causing this behavior, so
any ideas would be helpful.