On Mon, 28 Feb 2005 13:58:27 -0500, you wrote:
Does anyone have any information about this part?
I've been told that
it's a high performance microprocessor. I found it on what looks like a hex
size DEC card made by Spectra Logic Corp. I found a picture of one on the
net but it's not very good.
<http://www.cpushack.net/gallery/showimg.php?file=/chippics/AMD/29K/AMDAM29116DC.jpg>
Joe
The 29116 is a 16 bit microcoded processor. It includes the following major blocks:
3 port ALU
32 word of single access RAM (the register file)
1 Accumulator register
16 bit barrel shifter
16 bit priority encoder
Status logic and test structure
Instruction decoder.
Designed by the same people that did the 2901 and 2903 bit slice processors, this
device is NOT bit slice, and could not be cascaded. Like the bit slice processors, it
does require an external sequencer, such as the 2910, 29112, 29311, or 29331, as well
as a microcod memory (SRAM or ROM).
A significant departure from previous devices is the use of vertical rather than
horizontal
microcode. This lead to the microinstruction for the '116 being only 16 bits, and
many
systems had a total microcode width of 32 bits, the other 16 bits being for a sequencer
such as the 2910, plus other control lines.
The original bipolar 29116 was designed by Bill Harmon. I was the design manager for
the CMOS version the 29C116 (I didn't do much, as the redesign was pretty much cut
and
paste). Other major players included Sunil Joshi, Deepak Mithani, Steve Stephansen,
Paul Chu (my boss. His boss was Bill Harmon), Brad Kitson, Warren Miller, and many
more that I can't remember. Please forgive me, it was 18 years ago.
Typical applications included disk/tape/printer controllers, graphics engines, missile
guidance computers, telephone switching systems (PABX/PMBX) and generally other
16 applications that previously used 4 x 2901 or 4 x 2903 type devices.
The standard software tools were either AMDASM from AMD or StepASM from Step
engineering. These were highly configurable meta-assemblers, with extensive macro
capabilities. There were no higher level languages.
Typical system cycle time was around 140 nS, the CMOS version was somewhat faster.
Philip Freidin
Ex Manager of Product Planning for Microprogrammable Processors at AMD
=================
Philip Freidin
philip at
fliptronics.com