Hi all,
I don't know why, but my mails seem to delay at least 30 hours before
they appear on the list. I have sent an update on my troubleshooting
findings and a reply on Julian's e-mail about the Flip Chips, *all*
yesterday (writing this e-mail Friday morning ...).
Anyway, here are my new findings, and conslusions.
On diagram KY-4, I checked the address decoder E34, and the 74154.
As expected, the outputs KY4 LD REG 0H and KY4 LD REG 1H are active
(otherwise keypad scanning and the display would not work at all).
The address decoder also puts out select signals to the RAM and
the 'KY ROM 2 EN L'. At first, I did not see any pulses on the output
'KY4 ROM 1 EN L', and I thought "AHA"! Too early, but that's OK!
I grabbed the 8008 code source listing and checked. ROM 2, E33/E39
on page KY-2 are almost continuously addressed, because the monitor
program loop sits in these 2 ROMs (address range 000-777 octal).
Checking the listing, I see that the first code in ROM 1, E3/E21,
is the processing of the LSR button, and the code comment actually
says "turn on SR DISP". When I press the LSR button, both ROM 1's
are addressed.
My conclusion is that all 4 ROMs are OK, as is the address decoder
(which is also a ROM) and the 74154 (all with the associated logic).
On page KY-1, the 8008 state output lines, S0, S1, and S2, go to
a 7442 decoder. The documentation explains the decoded states, and
mentions that pin 2 of the 7442 ('KY1 STOP L') is asserted when the
8008 crashes (in fact, when the 8008 executes a HALT instruction,
which is octal 0, or 1, or 377). When STOP L is activated, the 8008
will restart itself. I scoped pin 2, and can say that 'STOP L' is
never asserted.
That means that the 8008 is continuously executing its program,
without any restarts. The clock signal at TP1 is a nice square wave
with a duty cycle of approx 50%, cycle time a bit more than 1 uSec.
From the above I conclude that more parts are
functioning correctly:
- the 8008 CPU + clock and power-up/restart logic
- the transceivers E16/E17 that buffer the multiplexed addr/data bus
- the 2 RAMs (E11/E27)
- the 4 ROMs (E3/E21/E33/E39)
- the address latches (E5/E4) because they buffer the ROM addresses
- address decoder ROM (E34)
- "register" selector 74154 (E48)
It is time to find out why only the 3 lsb displays flicker brief
when I press a button, and why the msb 3 displays do not react at all.
I also saw that sometimes the RUN LED is turned on.
Pressing the CNTRL (only that button!) the BUS ERR LED goes on (???).
Normally CNTRL must be used in conjunction with another button ...
Pressing CLR makes BUS ERR turn off.
Also, I noted that at some point the display showed "666666", but I
can not change the value. For now, I am not too worried about this.
I contribute this behaviour to the less-than-perfect contacts, now
that the M7859 is on top op 2 dual width extender boards (so that I
can probe pins of the ICs on the M7859).
Again, any comments or hints are highly appreciated!
- Henk, PA8PDP.
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