Sean 'Captain Napalm' Conner wrote: that's baby stuff! :-) UNC worked for many years on a chip architecture called pixel planes. they developed a few generations of custom VLSI chips for it. anyway, everything inside was bit serial and was controlled by SIMD instructions. one chip controlled a 128x128 group of ALUs, and each ALU had something like 2 kbits of DRAM. sure, that is only 16K processors -- but that was just one chip. they had 256 or so of these chips on a board, and had 16 or so boards in a rack, and their system had something like 6 racks. the SIMD'ness was only local to a chip -- they didn't have all the ALUs in the system driven by one instruction stream! because of the scale of the thing, they had to worry about clock skew, as all of these boards were communicating over a token ring bus (not IBM's token ring -- their own). their solution was interesting. their backplane boards had a clock plane that was driven from one side, and the other side was unterminated. they picked their geometry and frequency such that they would set up a standing wave and the antinodes of the wave were coincident with where each board was plugged in. although it was primarily used for graphics, there were some attempts at using it for more general computation. anyway, I saw it (pixel planes 5) in operation at siggraph in 93 I think. they were giving away buttons saying "I saw it!", referring to the fact it was doing 2M phong shaded triangles in real time. It was amazing for the time, but now single GPU chips crank out 100x that many triangles that have much more complex shading.