That's the signal which tells the world that the Z-80 is starting a new instruction cycle and is currently fetching the opcode. It is also the cycle during which the refresh occurs. The Z-80 asserts IOREQ* and M1* concurrently in order to signal a vectored interrupt acknowledge is in progress and that the peripheral should drive its interrupt vector address onto the bus. Aside from this last functon, I've never seen any particular need for a processor to let me in on the fact its opcode fetch cycle was in progress. It is helpful, I guess, if you're hand-toggling a program into the processor as it executes them, though that's not how it's usually done. Dick -----Original Message----- From: Arfon Gryffydd <arfonrg(a)texas.net> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Wednesday, March 31, 1999 7:36 AM Subject: Z-80 M1?