<A Z80 will give useful patterns executing continual 00 (NOP, so the <address bus cycles through all of memory) or FF (RST 38, so the stack <builds down to fill all off memory). Both should provide useful patterns <on DRAM control lines. Indeed they do. If you want to force a pattern, the inbound bus buffer can have pins lifted (if socketed). There are pleny of tricks before getting out the "big guns". For the cannons for ants set I do have a S100 Bus debugger that was use use the phrase purpose built. It's a Logic analyser that has 4 leads floating and 32 (address and datain plus data out) and a riot of controls so that it's possible to do a bus level logic analysis and it has 16kx40bits of 2167 55ns ram to take a extended picture of things. I built it to deal with the quad processor system as there were a lot of signals running. <Like Allison I used to work almost entirely with a logic probe and a VOM <(and a brain, which is the most important 'instrument' of all :-)). I had <a good logic analyser, which saved me a lot of time on occasions, but it <wasn't that convenient to use. I have a 16 channel LA and two good scopes but often as not if I poke and think as Dwight sugggested I rarely need to drag them out and set them up. The most common use for the LA is craking "black box" devices and chips. <I rarely use a 'scope for computer (digital) repairs. It's essential for <analogue work, fixing SMPSUs, etc. But I don't find it _that_ useful on <typical non-repetitive digital signals. Depends, very handy for looking at some timing problems and general bus havoc. <Don't bet on it. I've lost count of the number of misdesigned (often <subtly - like marginal timing or ground bounce problems) DRAM cards that <I've had to sort out. Those cards never worked, as in they often were unreliable or at best a question. S100 cards generally were either solid or sick to my expereince. It may have required running them for a day or two to see that they were not good 24x7 designs. <Also, a logic probe won't detect _some_ chip failures. You've got a 2 <input NAND gate. The logic probe shows nice pulse trains on all 3 <connections. You think it's OK and move on. What it hasn't told you is <that one input does nothing, and the gate is a simple inverter on the <other input. Yes, I've seen exactly that fault. Same here, bad inputs are tough to shoot, though a chip clip (16pins 16 leds) does help here. Allison