Den tis 26 jan. 2021 kl 22:39 skrev Paul Koning <paulkoning at comcast.net>:
On Jan 26, 2021, at 2:35 PM, Mattis Lind
<mattislind at gmail.com> wrote:
Hello Paul,
...
> The framing is different but no harder, I think. And I was thinking of
leaving the protocol state machine to the host, so the microcontroller
would only do framing -- deliver completed good frames to the host without
interpretation.
I
made a very quick check on DDCMP. It looks a bit like BSC but using a
byte counter
rather than various characters to end the frame. That would
probably simplify the software. It seems to use SYN SYN which is identical
to BSC so that part of the code that takes care of framing could probably
be used directly.
Yes, though the sync byte has a different value, the fact that it's called
SYN is a bit misleading if you're used to the SYN used in BISYNC.
Right. That should be quite simple. A #define and then in the SyncFSM.cpp
this line need to be changed: "if (((dataWord >> i) & 0xffff) == 0x4c4c)
{"
0x4C is the SYN byte (0x32) in reverse bit order.
There are also the small STM32F411 Weact boards out
there (
https://github.com/WeActTC/MiniF4-STM32F4x1). 100 MHz and the ART
accelerator. From other projects where I have used the STM32F103 have seen
that it executes slower than I expected since it was reading code from
flash. The ART accelerator should help here to achieve near zero wait state
so perhaps 1 Mbit/s would be possible?
What is an ART?
ART is a ST term for some kind of cache mechanism that allows the processor
to run at near zero wait state. Normal INTERNAL flash accesses have wait
states. Flash is slower than RAM even when on chip. As far as I understand
this ART feature is not available on the STM32F103. Which means that all
flash-accesses will have two wait states when running at 72 MHz. I just
discovered this when trying to optimize the inner loop of the SCSI
handshake in my fork of ArdSCSIno (
https://github.com/MattisLind/ArdSCSino-stm32). The 30 instructions that
were to be executed took much longer than I expected.
Looking at the Microchip ATSAMD51 of the ItsyBitsy board it seems that it
has a TCM (Tightly Coupled Memory) that can be used as a cache similar to
the ART function.
I looked a bit at that Weact thing but got lost in the
fulminating about
"pirated" copies. Seriously? Open source designs are meant to be copied;
"pirated" is a nonsensical term. Low quality copies, that would be a valid
complaint. (The use of leaded solder, all things equal, increases quality
rather than reducing it, by the way.)
I really don't think that WeAct say that it is "Open Source". Do you see a
license saying it is Open Source?
My focus is on the chip on the board not the manufacturer. The WeAct board
is almost pin compatible with the STM32F103 blue pill board while having an
STM32F4 chip (which has more of everything compared to the STM32F1). So I
decided to use only pins that had exactly the same function on both Blue
Pill and WeAct boards so that one could change to the WeAct board without
redesigning my board.
The ARM chips used in the Adafruit boards I've used have on-chip flash so
I'd assume that runs quickly, but I'll have to try to find out.
No, It also has wait states. But the TCM can be used as a cache as far as I
can see from a quick check. I am by no means an expert on this. I just had
a quick look right now. (
https://github.com/adafruit/ArduinoCore-samd/issues/37)
All ST ARM chips have on-chip Flash as well, no difference there really.
But flash is inherently slower.
.
...
If you have further questions feel free to ask. Would be nice to add
DDCMP support
as well! Then perhaps I could try those M8203 / M8207 boards
I have sitting here.
Thanks, will keep that in mind. What sort of connection and signaling do
your DMR boards use?
Not really sure.
http://forum.datormuseum.se/item/6E7AA955-997A-4568-B181-843BD5AC1321.html
http://forum.datormuseum.se/item/33D8D630-0CDD-4D92-A148-06F88644BA17.html
I don't have DEC connector kits to go from 40 pin BERG to something else.
/Mattis
paul