"Ben Franchuk" &lt;bfranchuk(a)jetnet.ab.ca&gt; wrote: ... 't seems to me that there are several free HDL's of the 650x core out there, and, since they're small, there are several FPGA's into which I understand you can fit not only four or so cores, but the entire addressable memory space for each of them in there as well. I've not tried that ... but ... The 650x core is apparently known to be about 3300 gates, if you can go by their putative gate count. However, you can check 'em out for yourself. Google will turn up several. As you might expect, the Z80 core is quite a bit larger and runs somewhat slower. I don't think anyone's done the 650x core "right" yet, because most of the HDL's still are too big. I remember the trade (~1976-77) mag's telling us that the 6502 was <1/4 the size of the Z80 though they were in the same technology. The only way I can see that happening, aside from the vastly reduced internal resources that the 650x has, is a much slicker design. Of course the end user doesn't benefit from that "slick" design, but if the thing's in mass production, the cost reflects silicon by the pound, so a smaller chip would cost less, which it did, while yielding more profit, which it apparently also did. Dick ----- Original Message ----- From: "Ben Franchuk" &lt;bfranchuk(a)jetnet.ab.ca&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Monday, December 17, 2001 1:47 AM Subject: Re: MITS 2SIO serial chip? It's SMsC, BTW. > > I hate sockets and try to avoid them, I've had equipment that > > didn't use the machined pin sockets and most all had to be > > rebuilt sans sockets at one point or another. > In this case I plan to use good sockets. > > A lousy one if you have a raft of TTL and few FPGAs. ;) > > All the TTL is in the FPGA.:) > Most of the TTL used is simple buffering or decoding. > > > I have a few of the Lattice and Xilinx tools, older ones and the synario > > stuff too. I just dont get all that excited about it. I've designed a > > cpu and built it years ago, it out of my system and not worth repeating. > > The whole point of the cpu I designed, was because I am not happy > with 8 bit micro's, RISC machines, or INTEL. Now what I wonder about > is people that put a 6502 in a FPGA while you still can buy the real > thing? > > Any cpu I'd do would need software and that means it would likely > > be a copy of something... likely something I have. > > I can guarantee you don't have a 12/24 bit cpu like mine. ( Not that you > would > want one :) ) > > Allison > -- > Ben Franchuk --- Pre-historic Cpu's -- > www.jetnet.ab.ca/users/bfranchuk/index.html > >

I may have to go out looking for a different one ... that's not the one I was thinking of when I wrote the item below, as that one spelled it out in terms of fitting in a specific Xilinx and in a particular Altera part as well as the associated clock rates. The ones that come in a PLCC-84 are still pretty small, though. Frankly, I'd prefer a much larger array in a PLCC-44 since one doesn't need pile of I/O, but the die size makes 'em use a big package to accomodate whatever sort of lead frame or whatever they use now. BTW, if you think you can buy that 65C02 from WDC any more, good luck, as I've never even been able to get them to quote on their fast part. They claim it runs at 20 MHz, but spec it for 14. Now 14 is pretty fast ... If you want fast, though, Dallas is sampling their 50MIPs 8051 part (89C420). They've redesigned the core so it uses one clock tick per instruction cycle, and most of the instructions that operate internally use only one cycle. The timer and external memory accesses, however, can be slowed down so (1) you don't have to use a 16-bit timer as a baud-rate generator, and (2) you can use slow external devices if you need to. It has promise! Dick ----- Original Message ----- From: "Ben Franchuk" &lt;bfranchuk(a)jetnet.ab.ca&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Monday, December 17, 2001 4:28 AM Subject: Re: MITS 2SIO serial chip? their will and yet, size that has,

see below, plz Dick ----- Original Message ----- From: "Ben Franchuk" &lt;bfranchuk(a)jetnet.ab.ca&gt; To: &lt;classiccmp(a)classiccmp.org&gt; Sent: Monday, December 17, 2001 3:35 AM Subject: Re: MITS 2SIO serial chip? I mentioned this only because SMC (later SMsC) made licensed replicas of most of the WD FDC parts and sold their all-digital technology to Western. There's nothing to tweak, since it's all-digital, and, eventually, but not this week, I can probably send you a scan or a PDF of the datasheet. The original I have is a preliminary, but I might still have a datasheet from the ChipCenter or Freetradezone. What I really like is that there is no need at all for cable drivers, since the interface lines are intended for direct connection. All you have to do is synchronize your CPU/DMAC to the data acquisition loop and then roll. If you're slow, you may want to use wait-states, but if you have no dificulty getting around a 13.5 microsecond loop (the first pass only) and 16 microseconds per byte, then you're in.