TTL homebrew CPUs - test-drb@ccmp.vtda.org

8 Jul 2007

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Subject: Re: TTL homebrew CPUs
   From: woodelf <bfranchuk at jetnet.ab.ca>
   Date: Sun, 08 Jul 2007 16:06:02 -0600
     To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>

Allison wrote:

  If I were to do a TTL design right now I'd
use 32Kx8 
 (or larger) parts even if the word size were 9 or 11 bits 
 as they are cheap and easy to use and the unused excess bits 
 are no real loss.   
11 Bits ???  What uses that? 
Nothing I know of but theres no reason in the world to say that
could not be done.

...
   Maybe because
every time I did TTL or slice design I wasn't 
 trying to make a period machine or be faithful I was doing 
 some sacrelige but I was having fun and the expereince was 
 no less because the memory, logic used or terminal was 
 way out of period. 
If this your hobby , the main thing is to have fun. 
Roger that! ;)

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  Heck the guy that did the Apollo AGC has a hats
off to me as
 he did in TTL something conceived as RTL with minimal data.
 If anything not only was a working machine a significant
 accomplishment but the information about it he dug up, made 
 visible to public and preserved along the way speaks to 
 great work. 
That was great work. 
I admire just finding all the data.  That was a easter egg hunt
if there ever was one.

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 For those that try and or succeed to build a PISC 
 (Pitiful Instruction Set Computer) or a VSC (Very 
 Simple Computer) they are contributing a lot to the 
 science and history of computing.  After all there 
 are many old (really old) machine preserved and sitting
 that most of us have not the first idea how to power 
 up and program.  Those that do it get my attention for 
 their efforts. 
The Kenback 1 and the 6800 replica's that come
up is great work too. I wish I could get him
to do my cpu from my hen scratched schematics.
Now the biggest problem I have is do I want
Single Instruction or not with my minimal front
panel?  Is that used that often that it needed?
Ben alias woolelf 
I have only done one front pannel, it was as much or more 
work than the CPU.  It's all the wires and as I like to call 
it "drillin and blastin".  So generally I try to avoid that
or do a very minimal one for debug rather than show.

The choice of what to build is always tough as there are 
so many choices.  In the end I started with very simple 
state machines and microprogrammed controllers and gradually 
decided what capability was missing and how best to achieve 
it based on what I knew and had done.

Whats funny is it's easier to design a slower wide word 
(32 or more bits) machine (lots of the same stuff repeated) 
than faster narrow word (8bit) machine.  Then you get into
variable word length or fixed, single address or multiple,
register or memory based, microcode or random logic control,
CISC or RISC.  In the end whatever is built you're not going
to be condemmed as at least it was built.

...
 PS. How are IRQ's handeled when single stepping?

Slowly. ;)  Single stepping would just mean if there was
an INT pending you would see all the steps and the adress
changes involved.  Or as I was told once, "Your the engineer,
what do you want it to do?".

Allison

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