Subject: Re: FPGA VAX update
From: woodelf <bfranchuk at jetnet.ab.ca>
Date: Sun, 23 Oct 2005 16:26:04 -0600
To: General Discussion: On-Topic and Off-Topic Posts <cctalk at
classiccmp.org>
Allison wrote:
70ns was 1982 tech level. Tech for 1995 was 25ns
for memory.
Current is under 1ns.
Don't forget one of the features of current hardware is the 1ns/ft
barrier is outside the chip.
The current CPU design barrier for me is the Beer Budget I have.
This gets me 70 ns memory and 20 ns/logic cell programable devices
and standard slow I/O devices. In 1982 I used a PDP-8/e so that
is a speed I am looking at. 1985 an XT.
Lets just say FPGA design is 1 generation slower than the latest
techology. From what little I have seen of custom design as the
designs shrink ( I still think in terms of 5 volt TTL ) layout rather
than switching speed is what will slow you down.
Well on my less than beer budget (I'm cheap) The static 32k byte devices
I've pulled off of old 386 and 486 board are 25ns and below.
Now he typical 30pin simms are 70ns dynamic rams. The core for PDP-8e
generation was the limiting factor at 1.5uS or more than 20 times slower.
The FPGAs I was playing with are as fast as late 70s TTL so there is
no reason I cant do a faster PDP-8 with "old stuff". Then again the
PDP-8e was limited by the 1970s tech of core speed not logic speed
it could esily go faster if core could keep up. The mid 80s 6120
(Decmate II and III) CMOS pdp8 chip was faster too despite being
microprogramed and multiplxed bus.
However if your assumption that FPGA is one speed generation behind
current silicon that makes it still under 1ns/cell which is plenty fast.
Granted there is some speed penelty for nonoptimum routing.
People that have done PDP-8s in FPGAs easily exceed the basic 8e speeds
save for they don't seem to push them at all.
As to the 1982 XT, that was slow by then standards by a factor of not
less than 2. In 1982 the 8086/88 was up to 10mhz already.
Allison