17 Jun
2011
17 Jun
'11
10:27 p.m.
On Sat, Jun 18, 2011 at 12:55 AM, Chuck Guzis <cclist at sydex.com> wrote:
On 17 Jun 2011 at 23:07, Dan Roganti wrote:
hope my ascii schematics still works (using courier font)
DeMorgans Theorem
Positive Logic <----> Negative Logic
_______
+-----\ \ \
A >-------| \ A>----O\ \
| AND |-->C | AND O---->C
B >-------| / B>----O/ /
+-----/ /______/
(bubble inputs & outputs)
A B C A B C
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 True State <--SAME--> 1 1 1 True State
_______
+-----\ \ \
A >-------| \ A>----O\ \
| NAND O-->C | NAND ----->C
B >-------| / B>----O/ /
+-----/ /______/
(bubble inputs only)
A B C A B C
0 0 1 0 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 True State <--SAME--> 1 1 0 True State
======================================================
Negative Logic Design
Positive Logic <----> Negative Logic
_______
+-----\ \ \
A >-------| \ A >-----\ \
| AND |-->C | OR ---->C
B* * >-------| / B >-----/ /
+-----/ /______/
A B C A B C
0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 True State <--INVERSE--> 0 0 0 True State
_______
+-----\ \ \
A >-------| \ A >-----\ \
| NAND O-->C | NOR O--->C
B* * >-------| / B >-----/ /
+-----/ /______/
A B C A B C
0 0 1 1 1 0
0 1 1 1 0 0
1 0 1 0 1 0
1 1 0 True State <--INVERSE--> 0 0 1 True State
=Dan
I guess another basic way to describe is this
way
A positive Logic AND gate is the equivalent to a Negative Logic OR
gate. It's not the bubble input/output OR gate that you see when using
DeMorgan theorem.. So the true state in a AND gate is inverted when
you're using the OR gate.
It's *exactly* the DeMorgan equivalent. One assumes that all logic
levels have a bubble associated with them, so you don't make it
explicit. It's just a convention--"1" can be light off, with
"0"
light on. Or a given phase difference in an AC signal or "1"= tomato
soup and "0"=cream of mushroom. Some of the old databooks (I can't
recall which) used to show logic gates both ways for reference.