12 Nov
2005
12 Nov
'05
3:55 p.m.
Allison wrote:
I just did that with the LS design ... dropped down from 40 to 26 chips
for 2 bits.
Oh wait I was to buy FOOD today ... not doodle on quad paper. :)
This is 18 bits
... 2 or 3 or 6 or 9 is needed here, not 2 or 4 or 8
or blah! 16 :)
So throw away the excess bits. It's still cheaper. Also there is a
Single full adder TTL part the 7480.
Well the punch is ahrd but a HS reader is trivial to
build AS it's
been done many times.
I guess I'll just have to use a ON-LINE punch then...
as to putting it CPLD or FPGA, yes you could but
I'm saying/staying in
TTL with available SSI and MSI functions it's possible to be chip count
reasonable.
I have nearly 30 IDE drives all under 500mb I can build around. Its
easy to make them look like a RK05 or whatever to a PDP-8 databreak
interface. What MS does next year or even lsat years does not impact
me at all.
But my CPLD software allways needs a new download ...
Ah foo.
PS. with the MATURE LS line of products, who knows what will be
produced in 5 years.
Allison
.