25 Mar
2002
25 Mar
'02
2:20 p.m.
On the subject of dual data pointers, Dallas did it wrong. I talked to the
engineers when they were designing this part, and ran the idea past them,
and it turned out they couldn't do it because it wasn't thought of
internally, even though I was willing to sign off all rights to it.
In the DPTR select register, the low order bit specifies which of the DPTRs
is used for MOVX, MOVC, and INC. However, if you try to integrate the
second data pointer into an existing code base that uses interrupts, you're
screwed. You have to modify all the interrupt routines that use the DPTR to
PUSH DPS, mov DPS,#0 (or 1), then POP DPS at the end. This wastes
instructions.
Instead, the DPS register should have caused the DPH0/DPH1 and DPL0/DPL1
pairs to be swapped. Most code has little care which DPx0/DPx1 pair is
being used. Typically, DPTR0 is used as a source register, and DPTR1 as a
destination register, and the DPS is incremented between the load and store
instructions. You don't care that DPH0 is at 80h and DPH1 at at 83h (or
where it's actually at, book isn't handy).
With my method, existing interrupt code wouldn't break, because when it
does the PUSH DPH, the DPH for the current DPTR would be pushed, because the
current DPTR would always be mapped into 80h/81h, as if you had one DPTR.
This allows new code to be written to use the dual data pointers, while the
existing object code (as in the case of linkable libraries from 3rd party
vendors) won't break.
But no, they screwed that up royally.
--John
-----Original Message-----
From: owner-classiccmp(a)classiccmp.org
[mailto:owner-classiccmp@classiccmp.org]On Behalf Of Richard Erlacher
Sent: Monday, March 25, 2002 21:06 PM
To: classiccmp(a)classiccmp.org
Subject: Re: Source code for 805x line-by-line assembler?
I'm not really familiar with the DS5000, but ISTR that it simply
does what I
do in external hardware, i.e. map the lower RAM into code space
and the upper
RAM in to data space. Because it's still the RAM, it's still
writeable. I
know they have some security related operations they do to
protect the memory
form external view, but as I've said before, it's not rocket science. It
involves a hardware trick because they can't simply make it
inherent in the
processor, because they then sacrifice the compatibility with other 805x
types.
The 89C420 is quite different from most of the 805x types, first in that a
single-cycle instruction takes only one system clock cycle (
which can be 1x,
2x, or 4x the oscillator frequency up to a maximum of 50 MHz) and
there modes
it can operate in that greatly accelerate external memory
accesses, again, up
to the 50 MHz limit.
I find this part quite irresistable, first because of its speed, but, more
importantly, because of the high quality of the no-cost tools
supporting it at
least generically. This particular part has two data pointers,
like several
of the Dallas 805x extensions, and it has two serial ports, one
of which is
capable of supporting a multi-drop network interface. It has control bits
that emable it automatically to increment/decrement one or both
of the data
pointers as part of an indirect read or write, and it has those
interesting
external memory interface modes, plus built-in cycle stretching logic, for
increasing speed and compatibility with slower devices than the
fast bus would
otherwise support. Additionally, it has 16KB of on-board FLASH
memory, though
that's limited to 33 MHz system clock when if you use it, and it
has an extra
1K of SRAM on board that can be used either in code space or in
data space.
Frankly, the feature set is staggering. As all of the 805x
family members, it
has separate code and data space, each 64KB in size, but because you can
twiddle the internal ROM size parameters, you can actually have
an 80KB code
memory space, witht the 16KB of on-board FLASH memory enabled or disabled,
selectively, or mapped where it can be used, say, as moveable tables.
It's amazing! It's so flexible, I'm looking for a filesystem to
use with it
so it can be its own independent development tool, at least for
in-the-field
patching.
Dick
----- Original Message -----
From: "Douglas Quebbeman" <dhquebbeman(a)theestopinalgroup.com>
To: <classiccmp(a)classiccmp.org>
Sent: Monday, March 25, 2002 8:34 AM
Subject: RE: Source code for 805x line-by-line assembler?
> 805x processors cannot (without external
hardware) write to program
memory,
so any
> line assembler would be dependant on some (common) hardware tricks to
write
to
program space.
Although I keep some Intel parts around, I prefer the Dallas
Semiconductor DS5000 familiy, which allows software to partition
its 64k memory between code space and data space.
However, I'll grant that this qualifies under your definition of
"hardware tricks", even though it's not quite what you had in mind.
Regards,
-dq