13 Dec
2005
13 Dec
'05
10:34 p.m.
Gooijen, Henk wrote:
but it would make the entry of an address (16-bit)
cumbersome.
You must enter it as an 8-bit high and an 8-bit low address.
I'd definately would go for 16 switches in this case, and also
16 LEDs for the address. Perhaps a matter of taste ...
But come to think of it,. was not the 6809 board first designed for your
PDP 11 interface?. More than ample switches and lights.
What if you need access to xxx.nnn where xxx != 000 or 777?
Why pose limits that early in the design? You might regret such
a decision later ...
In my case most front panel work will be simple test programs or booting
from
rom in upper memory or testing I/O devices. Since the CPLD cpu data bus is
9 bits wide that is the width I have to use for address load from the
front panel
in the current design. I have 1 or two bits free for address select
switches that
can go into the control CPLD that can be sign extended into the PC. One goal
is have only 38 control and data i/o lines to emulate a fictional 40
pin dip.
6909 comes to mind for a phoney chip ID too.
So far I am using 2 CPLD's for the bit slices, and 1 CPLD for control.
A 4 th CPLD will be bus and I/O buffering. The remainder on the PCB is
some 6821's and 6850's as well as16kx9 static ram. Front panel leds are
driven by the bit slices. The design just fits in the CPLD's so I
don't think
I can experiment with the instruction set any more.
- Henk, PA8PDP