Oh!
VHDL is the ADA of EDA languages--almost no one ever
uses it because
they *want* to.
I adore it!
I find Verilog quite crappy. And it doesn't tell me when I misspell a signal. Ok,
perhaps a little
compiler warning - but that's all.
With VHDL I have a quite better chance to get a running design if it passes the
compiler...!
I like Verilog very much; it's straightforward
and
not too "dirty".
IMHO it *IS* dirty. VERY dirty.
Philipp .-)
--
http://www.hachti.de