24 Oct
2011
24 Oct
'11
1:01 p.m.
On Oct 23, 2011, at 3:17 PM, Tony Duell wrote:
Exactly!. At least with FPGAs thay can't (easily) use analogue monostable
circuits. This sort of designer let loose on TTL will thow '123s
everywhere without realising that if the timing components drift the
signals can change in the wrong order.
And then there are the FPGA designers who design
like this : THey'll
enter a scheamtic in the schematic capture program and simulate it. It
doens't work so they say things like 'let's invert that signal and see if
that helps. OK, it didn't, what happes if we change that AND to an OR?'
No real method, no logic to what they are doing. I've met them...
Oh lord, and then there's the ones who make a pipelined structure, but
can't be bothered to figure out when a timing-sensitive signal is
actually supposed to happen, so they just make a giant delay chain or And going back to circuit design, let's not forget
the folks who put
zener ESD protection on everything, including the input ferrite beads!
At least they ddin't put ferrite beads on the leads of the protection
zenrs, thus ensuring said zeners cna't catch a fast spike.
I guess this is the sort of person who puts a fuse in series with the
anode of a crowbvar SCR to protect it. Yes I did seee that one once, I
commented _before_ it got built, fortunately.
-tony