1 Mar
2015
1 Mar
'15
2:10 p.m.
On 2015-03-01 23:03, ben wrote:
On 3/1/2015 2:56 PM, Johnny Billquist wrote:
Uh... No. The timing in the PDP-8 is very specific to the PDP-8. A cycle
contains four states. Different operations in the CPU instruction
execution happens at different states. The length of each state is
specific to that state.
Admittedly, states in which memory is accesses were defined based on the
speed of core memory, but that is just a small part of the picture.
Some states only exists for certain instructions. Indirect
dereferenceing only happens if the instruction has the indirect bit set,
and the DMA state only happens if there is a DMA request active (or Data
Break as it was called).
The whole time state machine is built based on how the PDP-8
instructions work. It's far from as generic like you suggest.
I don't think so. On the PDP-8 at least, the
increment of the PC is done
at different clock phases for different reasons, and they are not
combined. I/O peripherals can also increment the PC, and it happens at a
defined time.
The clock state machine of the PDP-8 is somewhat complex compared to
more "modern" machines.
I suspect all of the classic machines of the 60's era, would have
similar timing since it was the split cycle of core memory the defined
your major timing states. Any how, Bitsavers has all the details where hard ware
manuals said more
that "Made in <country of the week>.
Yes. :-)
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt at softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol