TI 990 architecture

While a workspace point defining the location of a set of "registers" in main memory sounds like a good idea, is it? While one avoids the need for 16 words of on-chip register RAM, it comes at a cost of making an external memory access (not to mention an address calculation) each time a register is addressed (most of the instructions do this, so the cost in cycles is very high). It seems to me to be far better to employ the S/360 method of using STM/LM-type instructions to change the context. The multiple register load and store instructions are present on many other CPUs since then, but it seems that S/360 was the first to make use of this. While the in-memory "registers" could certainly be cached by the CPU (watch out for "dual" reference issues!), that seems to be less flexible than an architecture that allows any number of registers to be stored or loaded explicitly as part of a context switch. Thoughts? Cheers, Chuck