ZX Spectrum internals (Was: ZX81 kits)

On Oct 7, 2:17, Iggy Drougge wrote: to The Z80's special ability in handling DRAM is merely the presence of an on-board counter which increments once in every instruction cycle, and which is output onto the address bus once per instruction. This is only part of the requirement, however (see below). The refresh counter means the chip is guaranteed to cycle through the addresses (with no omissions) in a given period. This is exactly what you need for DRAM refresh. Of course, if you have a video circuit accessing the same DRAM, it too will cycle through the address range (or part of it) and achieve the same end, so the Z80 refresh is only a useful bonus if you don't have video accessing your DRAM. Anyway, it's only a 7-bit counter, which is fine for 16Kbit DRAM but not for most 64Kb devices. The downside is that a Z80 uses the clock in a different way from a 6502. A 6502 does some things on one half of the clock cycle (like accessing memory to read instructions or read/write data) and other things (internal operations) on the other half cycle. During the half-cycle when it doesn't need memory access, it releases the bus, leaving it free for use by other devices (eg video). A Z80 uses successive cycles (of a faster clock) instead of alternate half-cycles for different purposes and there is no clock state when it's guaranteed not to be using the bus. However, there is one (whole) clock cycle when it doesn't need the bus, and that's the refresh period; it's just more complicated to decode that than to just use the phase of the clock (high or low) to enable your video access (or whatever). It's also less suitable than the 6502 since Z80 instruction cycles vary in length and therefore the interval between refresh cycles is not constant. The interval between successive half cycles of a 6502 clock is (usually!) constant. I said the refresh was only part of the requirement. That's because DRAM normally splits the address into two parts, row addresses and column addresses, to address a given cell in the memory matrix. Usually these two parts of the address are multiplexed onto the same pins of the IC. Therefore, on the first part of the memory access cycle, you put the row addresses on the pins and signal this to the DRAM with the /RAS (row address select) signal. The IC latches these address bits internally, and after some time period, you turn off /RAS, replace the row address bits with the column address, and apply the /CAS signal. Neither the Z80 nor the 6502 have any special feature to simplify this (unless you count the fact that you have two clock phases per memory address on a Z80). So in a Spectrum, ZX81, etc, the ULA takes care of the address multiplexing and RAS/CAS timing. Just slang for the assorted logic that does address decoding, signal buffering, RAS/CAS generation, etc. In a typical system with, let's say, ROM, RAM, processor, some I/O ports, perhaps a DMA device, each section that connects to the address/data bus (and perhaps the control bus too, if DMA is involved) would have its own set of buffer ICs, each being enabled only when the relevant section is accessing the bus. The glue logic includes all the decoding/multiplexing of the address and control signals. If you think of a system as CPU, RAM, ROM, I/O ports, then the glue logic is all the extra circuitry you need to "glue" them together into a working system. work to it Sinclair never used sockets if they didn't have to, for reasons of both cost and reliability. If there was a special Sinclair-original ROM for Scandinavian countries, I would have expected that to be factory-fitted instead of the standard ROM. It's possible they retrofitted something like that -- it might be cheaper to piggyback a new ROM instead of removing the old one -- but I would guess that what you have is something done by the original owner, in order to have both systems. Sinclair would be most unlikely to fit something as extravegant as a switch. -- Pete Peter Turnbull Network Manager University of York