23 Oct
2005
23 Oct
'05
4:49 p.m.
Tim Shoppa wrote:
I suspect that a FPGA implementation of a VAX would have a
performance about equal to a 11/780 if done by an average Joe.
Someone with much experience in caching/pipelining could probably
eek out a factor of 2x or 3x by pulling out all the tricks in the
book.
I have to disagree. I think you're off by at least a factor of 10,
maybe even 100.
http://www.fpgacpu.org (and that's 3 year old info)
If you can build a 300mips 8051 in an fpga, you sure as heck can build a
10mips vax. I would bet on 50mips w/o breaking a sweat.
http://www.opencores.org/projects.cgi/web/yacc/overview
that's 110mips @ 165mhz. not hard at all these days. heck, you run
the sdram interface at 100mhz.
If you can keep things inside the fpga you can use clock multipliers to
run pretty fast. It's the pad ring which will slow you down, but now
days the on/off chip delays are under 10ns.
I would think the sdram interface would be the limiting factor. You'd
want to burst into a cache but that eats up a ton of resources, so you
have to find a reasonable tradeoff.
There is enough ram inside most fpga's these days to do some form of
associative caching and all of the microcode/register file you need.
Go look at NIOS and other off-the-shelf cpu's. They are moving a long at
a nice clip.
-brad