29 Jan
2008
29 Jan
'08
7:42 a.m.
Subject: Re: 8-bit micro MMU's
From: Dave McGuire <mcguire at neurotica.com>
Date: Tue, 29 Jan 2008 01:19:35 -0500
To: "General Discussion: On-Topic Posts Only" <cctech at
classiccmp.org>
On Jan 28, 2008, at 3:02 PM, Chuck Guzis wrote:
Nothing save for the 8202 was optimized for 16k drams and the 8080
cpu (at 2mhz!). It was the older part. if your going to do Dram
larger than 64k that the 8203 is the part of choise and pretty decent
though not fantastically fast. the latter was because early Dram
didn't do cas/ before ras/ refresh and other tricks to interleve
the refresh cycle and the early parts were slow.
With the slow memory chips back then, making
things work with the
wretched 8202 DRAM controller was a real chore. I seem to recall
that if you ran worst-case numbers, you could wind up with the
requirement of a negative access time for the DRAM for a 5MHz 8085.
Adding bank-mapping hardware in the address path didn't improve
things any.
A slight diversion here...What is wretched about the 8202? I ask
because I got ahold of a few not long ago (and some 8203s) and was
considering putting something together with them to play with. I worked with the 8207 DRAM controller extensively
on the Navier-
Stokes Supercomputer Project at Princeton in the mid-late 1980s...We
had lots of problems with the memory arrays at first, but they were
eventually all traced to power...both nasty spikes on Vdd and ground
bounce.
Big arrays are tough in the power gridding and bypass. The 8207 was
a more involved part to use.
Allison
-Dave
--
Dave McGuire
Port Charlotte, FL