23 Oct
2005
23 Oct
'05
3:26 p.m.
Allison wrote:
70ns was 1982 tech level. Tech for 1995 was 25ns for
memory.
Current is under 1ns.
Don't forget one of the features of current hardware is the 1ns/ft
barrier is outside the chip.
The current CPU design barrier for me is the Beer Budget I have.
This gets me 70 ns memory and 20 ns/logic cell programable devices
and standard slow I/O devices. In 1982 I used a PDP-8/e so that
is a speed I am looking at. 1985 an XT.
Lets just say FPGA design is 1 generation slower than the latest
techology. From what little I have seen of custom design as the
designs shrink ( I still think in terms of 5 volt TTL ) layout rather
than switching speed is what will slow you down.
Allison