1 Jan
2009
1 Jan
'09
1:18 p.m.
On Jan 1, 2009, at 1:38 PM, Jim Battle wrote:
Very cool. Do you know if it is the complete machine? Any
schematics? How large is it?
It makes me wonder if it could be implemented on an FPGA. With
today's design languages, it wouldn't be very difficult to create a
tool chain that could turn a BNF description into a netlist -- BNF -
Oooh, that'd be serious fun!
Chapter 8 of "Advances in Computer
Architecture" describes the
SYMBOL computer, designed
and built buy Fairchild Camera, and operated at
Iowa State.
Only one was built.
And that one is in the CHM collection. I have found some
documentation for it, but no software. verilog, verilog->gates. I'm sure one
thing that was very
daunting back then was any small change to the language would
result in massive changes to the wiring. Of course there would be no reason for carrying it
out, but it is
fun to think about.
Nono, think of the architectural research that this would
facilitate! Aside from just being fun, one could do some seriously
interesting architectural work with something like this.
Even if you could build such an FPGA and got it going
at 100 MHz,
it would still be slower than a conventional compiler running on a
2 GHz x86. Despite the increased efficiency, it is hard to bridge
that 20x clock multiplier. The best you could do is improve on the
start up time, but for any code that iterated, the compiler would
win as the parsing costs are paid only once.
I dunno, those x86s are pretty darn inefficient.
-Dave
--
Dave McGuire
Port Charlotte, FL