23 Nov
2006
23 Nov
'06
6:57 a.m.
Roger Holmes wrote:
...
There is another class of simulation I have been
considering
lately.
...
it would be possible to write a
program which does a gate level simulation on a fast machine
like my 2GHz Mac.
I'm not trying to be a pain, but I'd call that verilog (or vhdl),
for which many fine compiler/interpreters exist.
You could even simulate the signals in
the machine, hook up a simulated oscilloscope and look at
the waveforms.
they do that as well. overshoot/undershoot requires something like
spice, however, which can be done but is more work because you need more
detailed/accurate models.
Could I OCR the old line printer listings of the
interconnection lists
and use them to build the simulator?
yes. I did that with the CADR. I cheated a little since I was able
to find the original CAD files and used those to extract a net list,
but all I had was a net list.
It's not hard to turn a net list into verilog which will simulate.
(well, for the purposes of this discussion. there are issues. let's be
kind however, and assume a synchronous design.)
Simulating the audio output (which is pulsed on most
conditional
branch instructions) is another issue I am thinking about. Modern
computers can obviously make the sounds, but how do I convert
from a live stream of speaker reversals into what a modern
machine needs?
as long as you don't need "real time", you can get the output into
a file and play it off-line.
-brad