6 Jul
2000
6 Jul
'00
2:19 a.m.
I have to take exception to your suggestion of making
a modified version of
your FPGA to generate test points. There are lots of flops in an LCA and
limited routing resources.
I agree here. My practice has been to route the design without the test
points and then use the low level editor to add what test points I could
without changing the layout/routing. Of course then you can't count
on the signal you wanted to test on being there and being routable to a
IOB. It's definitely a different world than 74 series logic.
Eric