8 Apr
2013
8 Apr
'13
9:07 a.m.
On 04/07/2013 03:20 PM, Toby Thain wrote:
That's odd, I seem to recall my handbooks claiming
lower latencies for
(Unibus?) core than the MOS products in the same range, but don't have
the right handbook to, uh, hand.
I don't know from UNIBUS, but the CDC 7600 used 270 nsec core, which, in
1969 was much faster than MOS. The 7600 used a 10-way interleave for CP
memory, which allowed for an effective 27.5 nsec cycle time. The PPs
didn't interleave memory and one quirk of the machine was that it was
possible for very tight loops to overheat a location in core, causing
parity errors. A fix was eventually used that effectively inserted a
"wait state" if any location was hit repeatedly too frequently.
The "exchange jump" on the upper CDC systems (6000 and 7000) used a
read-modify-write cycle to swap the contents of the registers with an
area in memory. It was the fastest way to save and reload the enire
register set (using non-privileged instructions was far more
time-consuming, due to an odd trick used to save and restore the first
register of a set--often used as a quiz to new programmers).
--Chuck