15 May
2006
15 May
'06
7:10 a.m.
der Mouse wrote:
For 64 bit memory (assuming you want to treat it as a 64 bit
entity) you need 7 bits (minimum) to "correct a single bit error".
Simple rule of thumb: the extra bits in some way need to be
able to tell you WHICH of the other bits is wrong. So, you need
log2(width) bits to specify one of "width" bits (e.g., 5 for
32 bits, 6 for 64 bits, 3 for 8 bits, etc.).
But, you also have the "all bits are correct" case which must
be conveyed. So, log2(width)+1 are required.
*How* those bits are used in the code words is up to the
particular code.
Usually the
terms "parity SIMM" or "ECC SIMM" are used for SIMMs with
36 data bits. If the extra 4 bits are used for parity or ECC depends
on the memory logic in the machine, not on the SIMM.
Except I don't think 4 extra bits are enough to do ECC on 32 data bits.
There simply aren't enough possible codewords to do even SEC, much less
SECDED. (SEC on 32-bit data words demands *at least* a factor of 32
extra codewords, to handle the single-bit errors (33, actually, to
include the no-error case). But 4 extra bits gives only a factor of 16
extra codewords.
For machines with 64-bit memory buses (machines which require
32/33/36-bit SIMMs but demands they be installed in pairs usually have
64-bit data buses), you have 64 bits of data and 8 additional bits,
which ought to be enough to do useful ECC, though I haven't worked out
a specific example code.