24 Jul
2014
24 Jul
'14
7:22 p.m.
On Thu, Jul 24, 2014 at 4:21 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
[1] The VAX11/730 also loads the CPU microcode at
power-up, but from what
I rememebr, ther eare some hardware features that optimise it for the VAX
instruction set. While it is possible to give it a differnet instruciton
set, I think it wopuld be a lot less efficient.
All of the microcoded processors DEC designed, whether they had
loadable microcode or only ROM, had hardware that was substantially
oriented toward the normal DEC macroinstruction set(s), and would have
been very inefficient at implementing other instruction sets. The
VAX-11/7xx series hardware was designed for efficient execution of
both VAX and PDP-11 instruction sets, but the other machines were
designed for a single instruction set only. Even the machines that
officially supported user-written microcode (PDP-11/03, PDP-11/60,
some VAXen) were generally unsuited to implementing entirely different
instruction sets, and user-added instructions were expected to have
similar structure to standard instructions. The Western Digital chip
set used in the PDP-11/03 was used for at least two other instruction
sets, the WD16 used by Alpha Micro, which was very similar to the
PDP-11, and the Pascal Microengine, which executed UCSD p-System
p-code. The latter was not a very efficient use of the
microarchitecture, and consequently the Pascal Microengine was not
much faster than the UCSD p-System running on the fastest
general-purpose microprocessors available at its introduction. Since
general-purpose microprocessors were evolving quickly, soon it was too
slow to be taken seriously.
Early on, it was very expensive to use fast RAM chips for a microcode
store, so DEC used bipolar PROMs except on relatively high-priced
machines (e.g., KL10 and KS10), and if serious bugs were found, the
microcode PROMs had to be replaced.
For the KS10, it was considered that the RAM chips used in the control
store were unreliable, so they did parity checking on the control
store, and if there was an error, the CPU would halt and the console
processor would reload the control store. They patented that:
http://www.google.co.in/patents/US4231089
The VAX-11/780 introduced the concept of patchable control store,
where most of the control store was PROM but there was a small amount
of patch RAM. Costs of high speed RAM declined quickly enough that
most later non-microprocessor VAXen used entirely RAM control store.
With the advent of VAX microprocessors, the larger die area required
for RAM vs ROM shifted the economics shifted back to favor ROM with a
small RAM patch area.