14 May
2004
14 May
'04
3:34 a.m.
On Fri, 14 May 2004 09:06:39 -0400
Brad Parker <brad(a)heeltoe.com> wrote:
yes, but you also need to worry about back-to-back
accesses by the
unibus cpu. the 'card micro' needs to be able to get in and do it's
magic between the unibus cpu's two cycles...
i.e. bus locking...
Sure. But when your CPLD is complex enough (or if it is a FPGA)
you can
implement the controler lookalike logic in the CPLD hardware. E.g. the
already mentioned fixed value read only bits in a read / write CSR.
--
tsch??,
Jochen
Homepage: http://www.unixag-kl.fh-kl.de/~jkunz/